文件名称:C_9
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100个经典vhdl编程实例，
第1例 带控制端口的加法器
第2例 无控制端口的加法器
第3例 乘法器
第4例 比较器
第5例 二路选择器
第6例 寄存器
第7例 移位寄存器
第8例 综合单元库
第9例 七值逻辑与基本数据类型
第10例 函数
第11例 七值逻辑线或分辨函数
第12例 转换函数
第13例 左移函数
第14例 七值逻辑程序包
第15例 四输入多路器......
-100 vhdl classical programming examples, No. 1 is the control port Adder first two cases of uncontrolled port Adder No. 3 Multiplier first four cases compared with the first five cases 2 Lu choice for the first six cases Register No. 7 cases shift register first eight cases consolidated for the first module nine cases seven-valued logic and basic data types No. 10 No. 11 cases function seven-valued logic function or defective Line No. 12 conversion functions No. 13 bits function section 14 cases 7 logic package No. 15 cases four multi-input devices ......
第1例 带控制端口的加法器
第2例 无控制端口的加法器
第3例 乘法器
第4例 比较器
第5例 二路选择器
第6例 寄存器
第7例 移位寄存器
第8例 综合单元库
第9例 七值逻辑与基本数据类型
第10例 函数
第11例 七值逻辑线或分辨函数
第12例 转换函数
第13例 左移函数
第14例 七值逻辑程序包
第15例 四输入多路器......
-100 vhdl classical programming examples, No. 1 is the control port Adder first two cases of uncontrolled port Adder No. 3 Multiplier first four cases compared with the first five cases 2 Lu choice for the first six cases Register No. 7 cases shift register first eight cases consolidated for the first module nine cases seven-valued logic and basic data types No. 10 No. 11 cases function seven-valued logic function or defective Line No. 12 conversion functions No. 13 bits function section 14 cases 7 logic package No. 15 cases four multi-input devices ......
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下载文件列表
100个ＶＨＤＬ例子
.................\100vhdl例子
.................\...........\10_function
.................\...........\...........\10_bit_to_int.vhd
.................\...........\...........\README.TXT
.................\...........\11_wiredor
.................\...........\..........\11_wiredor.vhd
.................\...........\..........\README.TXT
.................\...........\12_convert
.................\...........\..........\12_convert.vhd
.................\...........\..........\README.TXT
.................\...........\13_SHL
.................\...........\......\13_SHL.VHD
.................\...........\......\README.TXT
.................\...........\14_MVL7_functions
.................\...........\.................\14_MVL7_functions.vhd
.................\...........\.................\README.TXT
.................\...........\15_MUX41
.................\...........\........\15_MUX41.VHD
.................\...........\........\15_MVL7_functions.vhd
.................\...........\........\15_MVL7_syn_types.vhd
.................\...........\........\15_test_vectors_mux41.vhd
.................\...........\........\15_TYPES.VHD
.................\...........\........\README.TXT
.................\...........\16_MUX
.................\...........\......\16_multiple_mux.vhd
.................\...........\......\16_MVL7_functions.vhd
.................\...........\......\16_test_vectors.vhd
.................\...........\......\16_TYPES.VHD
.................\...........\......\README.TXT
.................\...........\......\TYPES.VHD
.................\...........\17_parity
.................\...........\.........\17_parity.vhd
.................\...........\.........\17_test_bench.vhd
.................\...........\.........\README.TXT
.................\...........\18_LIB
.................\...........\......\18_tech_lib.vhd
.................\...........\......\18_test_lib.vhd
.................\...........\......\README.TXT
.................\...........\19_test_194
.................\...........\...........\19_test_194.vhd
.................\...........\1_ADDER
.................\...........\.......\1_ADDER
.................\...........\.......\.......\1_ADDER.exp
.................\...........\.......\.......\files
.................\...........\.......\.......\.....\L1.rpt
.................\...........\.......\.......\.....\L2.rpt
.................\...........\.......\.......\.....\L3.rpt
.................\...........\.......\.......\workdirs
.................\...........\.......\.......\........\aa
.................\...........\.......\.......\........\..\ADDER.sim
.................\...........\.......\.......\........\..\ADDER.syn
.................\...........\.......\.......\........\..\Anal.info
.................\...........\.......\.......\........\..\Anal.out
.................\...........\.......\.......\........\WORK
.................\...........\.......\.......\........\....\Anal.info
.................\...........\.......\.......\........\....\Anal.out
.................\...........\.......\.......\........\....\BIT_RTL_ADDER.sim
.................\...........\.......\.......\........\....\BIT_RTL_ADDER.syn
.................\...........\.......\1_adder.acf
.................\...........\.......\1_adder.hif
.................\...........\.......\1_adder.mmf
.................\...........\.......\1_ADDER.VHD
.................\...........\.......\bir_rtl_adder.acf
.................\...........\.......\bir_rtl_adder.hif
.................\...........\.......\bir_rtl_adder.mmf
.................\...........\.......\bir_rtl_adder.tdf
.................\...........\.......\bit_rtl_adder.acf
.................\...........\.......\bit_rtl_adder.hif
.................\...........\.......\bit_rtl_adder.mmf
.................\...........\.......\bit_rtl_adder.vhd
.................\...........\.......\LIB.DLS
.................\...........\.......\README.TXT
.................\...........\.......\U2268397.DLS
.................\...........\20_test_159
.................\...........\...........\20_test_159.vhd
.................\...........\21_test_13a
..........
.................\100vhdl例子
.................\...........\10_function
.................\...........\...........\10_bit_to_int.vhd
.................\...........\...........\README.TXT
.................\...........\11_wiredor
.................\...........\..........\11_wiredor.vhd
.................\...........\..........\README.TXT
.................\...........\12_convert
.................\...........\..........\12_convert.vhd
.................\...........\..........\README.TXT
.................\...........\13_SHL
.................\...........\......\13_SHL.VHD
.................\...........\......\README.TXT
.................\...........\14_MVL7_functions
.................\...........\.................\14_MVL7_functions.vhd
.................\...........\.................\README.TXT
.................\...........\15_MUX41
.................\...........\........\15_MUX41.VHD
.................\...........\........\15_MVL7_functions.vhd
.................\...........\........\15_MVL7_syn_types.vhd
.................\...........\........\15_test_vectors_mux41.vhd
.................\...........\........\15_TYPES.VHD
.................\...........\........\README.TXT
.................\...........\16_MUX
.................\...........\......\16_multiple_mux.vhd
.................\...........\......\16_MVL7_functions.vhd
.................\...........\......\16_test_vectors.vhd
.................\...........\......\16_TYPES.VHD
.................\...........\......\README.TXT
.................\...........\......\TYPES.VHD
.................\...........\17_parity
.................\...........\.........\17_parity.vhd
.................\...........\.........\17_test_bench.vhd
.................\...........\.........\README.TXT
.................\...........\18_LIB
.................\...........\......\18_tech_lib.vhd
.................\...........\......\18_test_lib.vhd
.................\...........\......\README.TXT
.................\...........\19_test_194
.................\...........\...........\19_test_194.vhd
.................\...........\1_ADDER
.................\...........\.......\1_ADDER
.................\...........\.......\.......\1_ADDER.exp
.................\...........\.......\.......\files
.................\...........\.......\.......\.....\L1.rpt
.................\...........\.......\.......\.....\L2.rpt
.................\...........\.......\.......\.....\L3.rpt
.................\...........\.......\.......\workdirs
.................\...........\.......\.......\........\aa
.................\...........\.......\.......\........\..\ADDER.sim
.................\...........\.......\.......\........\..\ADDER.syn
.................\...........\.......\.......\........\..\Anal.info
.................\...........\.......\.......\........\..\Anal.out
.................\...........\.......\.......\........\WORK
.................\...........\.......\.......\........\....\Anal.info
.................\...........\.......\.......\........\....\Anal.out
.................\...........\.......\.......\........\....\BIT_RTL_ADDER.sim
.................\...........\.......\.......\........\....\BIT_RTL_ADDER.syn
.................\...........\.......\1_adder.acf
.................\...........\.......\1_adder.hif
.................\...........\.......\1_adder.mmf
.................\...........\.......\1_ADDER.VHD
.................\...........\.......\bir_rtl_adder.acf
.................\...........\.......\bir_rtl_adder.hif
.................\...........\.......\bir_rtl_adder.mmf
.................\...........\.......\bir_rtl_adder.tdf
.................\...........\.......\bit_rtl_adder.acf
.................\...........\.......\bit_rtl_adder.hif
.................\...........\.......\bit_rtl_adder.mmf
.................\...........\.......\bit_rtl_adder.vhd
.................\...........\.......\LIB.DLS
.................\...........\.......\README.TXT
.................\...........\.......\U2268397.DLS
.................\...........\20_test_159
.................\...........\...........\20_test_159.vhd
.................\...........\21_test_13a
..........