文件名称:DJDPLV_LWB
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利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计,不但具有较高的测量精度,而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量,在前端输入加整形电路即可。-use ultra-high-speed Hardware Descr iption Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be.
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基于FPGA的等精度频率计(论文版).doc