文件名称:verilog111
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第五章
......\adder4
......\......\adder4.v
......\BIT_OP
......\......\bit_op.v
......\decod3_8
......\........\decod3_8.v
......\demul1_4
......\........\demul1_4.v
......\DIVID_8
......\.......\divid_8.v
......\encod4_2
......\........\encod4_2.v
......\EQU_INEQU
......\.........\equ_inequ.v
......\EVEN_PARITY
......\...........\even_parity.v
......\fadd1_df
......\........\fadd1_df.v
......\HALF_ADD
......\........\half_add.v
......\major
......\.....\major.v
......\mul2_1_4bits
......\............\mul2_1_4bits.v
......\sht_l_r
......\.......\sht_r_l.v
......\adder4
......\......\adder4.v
......\BIT_OP
......\......\bit_op.v
......\decod3_8
......\........\decod3_8.v
......\demul1_4
......\........\demul1_4.v
......\DIVID_8
......\.......\divid_8.v
......\encod4_2
......\........\encod4_2.v
......\EQU_INEQU
......\.........\equ_inequ.v
......\EVEN_PARITY
......\...........\even_parity.v
......\fadd1_df
......\........\fadd1_df.v
......\HALF_ADD
......\........\half_add.v
......\major
......\.....\major.v
......\mul2_1_4bits
......\............\mul2_1_4bits.v
......\sht_l_r
......\.......\sht_r_l.v