文件名称:Example-2-2
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这些是verilog编程实例2,仅供参考-These are two examples of Verilog Programming for reference
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下载文件列表
Example-2-2
...........\StateCAD_Demo
...........\.............\SIMTUT_TB.HLF
...........\.............\SIMTUT_TB.REG
...........\.............\SIMTUT_TB.TMP
...........\.............\SIMTUT_TB.VHD
...........\.............\TUT.DIA
...........\.............\TUT.vhd
...........\.............\TUT_TB.HLF
...........\.............\TUT_TB.REG
...........\.............\TUT_TB.TMP
...........\.............\TUT_TB.VHD
...........\.............\_import.dmo
...........\源文件
...........\......\SIMTUT_TB.VHD
...........\......\TUT.DIA
...........\......\TUT.vhd
...........\......\TUT_TB.VHD
...........\示例说明.doc
...........\StateCAD_Demo
...........\.............\SIMTUT_TB.HLF
...........\.............\SIMTUT_TB.REG
...........\.............\SIMTUT_TB.TMP
...........\.............\SIMTUT_TB.VHD
...........\.............\TUT.DIA
...........\.............\TUT.vhd
...........\.............\TUT_TB.HLF
...........\.............\TUT_TB.REG
...........\.............\TUT_TB.TMP
...........\.............\TUT_TB.VHD
...........\.............\_import.dmo
...........\源文件
...........\......\SIMTUT_TB.VHD
...........\......\TUT.DIA
...........\......\TUT.vhd
...........\......\TUT_TB.VHD
...........\示例说明.doc