文件名称:rtl
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
(系统自动生成,下载前可以参看下载内容)
下载文件列表
rtl
...\verilog
...\.......\BUGS
...\.......\CVS
...\.......\...\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\eth_clockgen.v
...\.......\eth_cop.v
...\.......\eth_crc.v
...\.......\eth_defines.v
...\.......\eth_fifo.v
...\.......\eth_maccontrol.v
...\.......\eth_macstatus.v
...\.......\eth_miim.v
...\.......\eth_outputcontrol.v
...\.......\eth_random.v
...\.......\eth_receivecontrol.v
...\.......\eth_register.v
...\.......\eth_registers.v
...\.......\eth_rxaddrcheck.v
...\.......\eth_rxcounters.v
...\.......\eth_rxethmac.v
...\.......\eth_rxstatem.v
...\.......\eth_shiftreg.v
...\.......\eth_spram_256x32.v
...\.......\eth_top.v
...\.......\eth_transmitcontrol.v
...\.......\eth_txcounters.v
...\.......\eth_txethmac.v
...\.......\eth_txstatem.v
...\.......\eth_wishbone.v
...\.......\timescale.v
...\.......\TODO
...\.......\transcript
...\.......\xilinx_dist_ram_16x32.v
...\verilog
...\.......\BUGS
...\.......\CVS
...\.......\...\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\eth_clockgen.v
...\.......\eth_cop.v
...\.......\eth_crc.v
...\.......\eth_defines.v
...\.......\eth_fifo.v
...\.......\eth_maccontrol.v
...\.......\eth_macstatus.v
...\.......\eth_miim.v
...\.......\eth_outputcontrol.v
...\.......\eth_random.v
...\.......\eth_receivecontrol.v
...\.......\eth_register.v
...\.......\eth_registers.v
...\.......\eth_rxaddrcheck.v
...\.......\eth_rxcounters.v
...\.......\eth_rxethmac.v
...\.......\eth_rxstatem.v
...\.......\eth_shiftreg.v
...\.......\eth_spram_256x32.v
...\.......\eth_top.v
...\.......\eth_transmitcontrol.v
...\.......\eth_txcounters.v
...\.......\eth_txethmac.v
...\.......\eth_txstatem.v
...\.......\eth_wishbone.v
...\.......\timescale.v
...\.......\TODO
...\.......\transcript
...\.......\xilinx_dist_ram_16x32.v