文件名称:leg_source
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 641kb
- 下载次数：
- 0次
- 提 供 者：
- lumi*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
(系统自动生成,下载前可以参看下载内容)
下载文件列表
leg_source
..........\inst_code.txt
..........\leg.v
..........\leg_dcache.v
..........\leg_define.v
..........\leg_dpram_syn.v
..........\leg_icache.v
..........\leg_mem_arbitor.v
..........\leg_mult.v
..........\leg_rf.v
..........\leg_shifter.v
..........\leg_soc.v
..........\leg_soc_tb.v
..........\leg_tb.v
..........\stack_test.cr.mti
..........\stack_test.mpf
..........\trace.txt
..........\work
..........\....\leg
..........\....\...\verilog.asm
..........\....\...\_primary.dat
..........\....\...\_primary.vhd
..........\....\leg_dcache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_dpram_syn
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\leg_icache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_mem
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\leg_mult
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\leg_rf
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\leg_shifter
..........\....\...........\verilog.asm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\leg_tb
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\_info
..........\Workbook of LEG.pdf
..........\inst_code.txt
..........\leg.v
..........\leg_dcache.v
..........\leg_define.v
..........\leg_dpram_syn.v
..........\leg_icache.v
..........\leg_mem_arbitor.v
..........\leg_mult.v
..........\leg_rf.v
..........\leg_shifter.v
..........\leg_soc.v
..........\leg_soc_tb.v
..........\leg_tb.v
..........\stack_test.cr.mti
..........\stack_test.mpf
..........\trace.txt
..........\work
..........\....\leg
..........\....\...\verilog.asm
..........\....\...\_primary.dat
..........\....\...\_primary.vhd
..........\....\leg_dcache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_dpram_syn
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\leg_icache
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\leg_mem
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\leg_mult
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\leg_rf
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\leg_shifter
..........\....\...........\verilog.asm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\leg_tb
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\_info
..........\Workbook of LEG.pdf