文件名称:usingVHDLtoimplementUART
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利用VHDL实现的UART
..................\UART 源码 (lattice version)
..................\...........................\uart_vhdl_lattice
..................\...........................\.................\intface.vhd
..................\...........................\.................\modem.vhd
..................\...........................\.................\rxcver.vhd
..................\...........................\.................\txmitt.vhd
..................\...........................\.................\uart_5kvg_top.vhd
..................\...........................\.................\uart_an_lattice.pdf
..................\...........................\.................\uart_int_tb.vhd
..................\...........................\.................\uart_rxerr_tb.vhd
..................\...........................\.................\uart_rx_tb.vhd
..................\...........................\.................\uart_top.vhd
..................\...........................\.................\uart_tx_tb.vhd
..................\uart 源码 (Verilog).zip
..................\uart 源码 (VHDL).zip
..................\uart16550.tar.gz
..................\UART 源码 (lattice version)
..................\...........................\uart_vhdl_lattice
..................\...........................\.................\intface.vhd
..................\...........................\.................\modem.vhd
..................\...........................\.................\rxcver.vhd
..................\...........................\.................\txmitt.vhd
..................\...........................\.................\uart_5kvg_top.vhd
..................\...........................\.................\uart_an_lattice.pdf
..................\...........................\.................\uart_int_tb.vhd
..................\...........................\.................\uart_rxerr_tb.vhd
..................\...........................\.................\uart_rx_tb.vhd
..................\...........................\.................\uart_top.vhd
..................\...........................\.................\uart_tx_tb.vhd
..................\uart 源码 (Verilog).zip
..................\uart 源码 (VHDL).zip
..................\uart16550.tar.gz