文件名称:VHDL-six
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用VHDL语言实现六分频,并且已经通过编译和仿真。由此可举一反三,实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
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下载文件列表
work1
.....\devider.acf
.....\devider.fit
.....\devider.hif
.....\devider.mmf
.....\devider.ndb
.....\devider.pin
.....\devider.pof
.....\devider.rpt
.....\devider.scf
.....\devider.snf
.....\DEVIDER.sym
.....\devider.vhd
.....\LIB.DLS
.....\U0262126.DLS
.....\U1909818.DLS
.....\U5700705.DLS
.....\devider.acf
.....\devider.fit
.....\devider.hif
.....\devider.mmf
.....\devider.ndb
.....\devider.pin
.....\devider.pof
.....\devider.rpt
.....\devider.scf
.....\devider.snf
.....\DEVIDER.sym
.....\devider.vhd
.....\LIB.DLS
.....\U0262126.DLS
.....\U1909818.DLS
.....\U5700705.DLS