文件名称:usb2[1].0
介绍说明－－下载内容均来自于网络，请自行研究使用
usb源码下载，是基于windows开发平台的，通过FPGA加以仿真验证。可以进行数据的传输-usb download the source code is based on the Windows platform, to be adopted FPGA simulation. Can be the transmission of data
(系统自动生成,下载前可以参看下载内容)
下载文件列表
usb2[1].0
.........\usb_funct
.........\.........\bench
.........\.........\.....\CVS
.........\.........\.....\...\Entries
.........\.........\.....\...\Repository
.........\.........\.....\...\Root
.........\.........\.....\verilog
.........\.........\.....\.......\CVS
.........\.........\.....\.......\...\Entries
.........\.........\.....\.......\...\Repository
.........\.........\.....\.......\...\Root
.........\.........\doc
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\README.txt
.........\.........\...\STATUS.txt
.........\.........\...\usb_doc.pdf
.........\.........\rtl
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\verilog
.........\.........\...\.......\CVS
.........\.........\...\.......\...\Entries
.........\.........\...\.......\...\Repository
.........\.........\...\.......\...\Root
.........\.........\...\.......\usbf_crc16.v
.........\.........\...\.......\usbf_crc5.v
.........\.........\...\.......\usbf_defines.v
.........\.........\...\.......\usbf_ep_rf.v
.........\.........\...\.......\usbf_ep_rf_dummy.v
.........\.........\...\.......\usbf_idma.v
.........\.........\...\.......\usbf_mem_arb.v
.........\.........\...\.......\usbf_pa.v
.........\.........\...\.......\usbf_pd.v
.........\.........\...\.......\usbf_pe.v
.........\.........\...\.......\usbf_pl.v
.........\.........\...\.......\usbf_rf.v
.........\.........\...\.......\usbf_top.v
.........\.........\...\.......\usbf_utmi_if.v
.........\.........\...\.......\usbf_utmi_ls.v
.........\.........\...\.......\usbf_wb.v
.........\.........\sim
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\rtl_sim
.........\.........\...\.......\bin
.........\.........\...\.......\...\CVS
.........\.........\...\.......\...\...\Entries
.........\.........\...\.......\...\...\Repository
.........\.........\...\.......\...\...\Root
.........\.........\...\.......\CVS
.........\.........\...\.......\...\Entries
.........\.........\...\.......\...\Repository
.........\.........\...\.......\...\Root
.........\.........\...\.......\run
.........\.........\...\.......\...\CVS
.........\.........\...\.......\...\...\Entries
.........\.........\...\.......\...\...\Repository
.........\.........\...\.......\...\...\Root
.........\.........\syn
.........\.........\...\bin
.........\.........\...\...\comp.dc
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\.........\...\...\design_spec.dc
.........\.........\...\...\lib_spec.dc
.........\.........\...\...\read.dc
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\log
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\.........\...\out
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\.........\...\run
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\usb_funct
.........\.........\bench
.........\.........\.....\CVS
.........\.........\.....\...\Entries
.........\.........\.....\...\Repository
.........\.........\.....\...\Root
.........\.........\.....\verilog
.........\.........\.....\.......\CVS
.........\.........\.....\.......\...\Entries
.........\.........\.....\.......\...\Repository
.........\.........\.....\.......\...\Root
.........\.........\doc
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\README.txt
.........\.........\...\STATUS.txt
.........\.........\...\usb_doc.pdf
.........\.........\rtl
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\verilog
.........\.........\...\.......\CVS
.........\.........\...\.......\...\Entries
.........\.........\...\.......\...\Repository
.........\.........\...\.......\...\Root
.........\.........\...\.......\usbf_crc16.v
.........\.........\...\.......\usbf_crc5.v
.........\.........\...\.......\usbf_defines.v
.........\.........\...\.......\usbf_ep_rf.v
.........\.........\...\.......\usbf_ep_rf_dummy.v
.........\.........\...\.......\usbf_idma.v
.........\.........\...\.......\usbf_mem_arb.v
.........\.........\...\.......\usbf_pa.v
.........\.........\...\.......\usbf_pd.v
.........\.........\...\.......\usbf_pe.v
.........\.........\...\.......\usbf_pl.v
.........\.........\...\.......\usbf_rf.v
.........\.........\...\.......\usbf_top.v
.........\.........\...\.......\usbf_utmi_if.v
.........\.........\...\.......\usbf_utmi_ls.v
.........\.........\...\.......\usbf_wb.v
.........\.........\sim
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\rtl_sim
.........\.........\...\.......\bin
.........\.........\...\.......\...\CVS
.........\.........\...\.......\...\...\Entries
.........\.........\...\.......\...\...\Repository
.........\.........\...\.......\...\...\Root
.........\.........\...\.......\CVS
.........\.........\...\.......\...\Entries
.........\.........\...\.......\...\Repository
.........\.........\...\.......\...\Root
.........\.........\...\.......\run
.........\.........\...\.......\...\CVS
.........\.........\...\.......\...\...\Entries
.........\.........\...\.......\...\...\Repository
.........\.........\...\.......\...\...\Root
.........\.........\syn
.........\.........\...\bin
.........\.........\...\...\comp.dc
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\.........\...\...\design_spec.dc
.........\.........\...\...\lib_spec.dc
.........\.........\...\...\read.dc
.........\.........\...\CVS
.........\.........\...\...\Entries
.........\.........\...\...\Repository
.........\.........\...\...\Root
.........\.........\...\log
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\.........\...\out
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root
.........\.........\...\run
.........\.........\...\...\CVS
.........\.........\...\...\...\Entries
.........\.........\...\...\...\Repository
.........\.........\...\...\...\Root