文件名称:simple_spi
介绍说明－－下载内容均来自于网络，请自行研究使用
一个简单的ＳＰＩ ＩＰ核，SPI Core Specifications 可以从说明文档中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
-a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
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simple_spi
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下载文件列表
simple_spi
..........\bench
..........\.....\CVS
..........\.....\...\Entries
..........\.....\...\Repository
..........\.....\...\Root
..........\.....\verilog
..........\.....\.......\CVS
..........\.....\.......\...\Entries
..........\.....\.......\...\Repository
..........\.....\.......\...\Root
..........\.....\.......\spi_slave_model.v
..........\.....\.......\tst_bench_top.v
..........\.....\.......\wb_master_model.v
..........\CVS
..........\...\Entries
..........\...\Repository
..........\...\Root
..........\doc
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\simple_spi.pdf
..........\...\src
..........\...\...\CVS
..........\...\...\...\Entries
..........\...\...\...\Repository
..........\...\...\...\Root
..........\...\...\simple_spi.doc
..........\rtl
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\verilog
..........\...\.......\CVS
..........\...\.......\...\Entries
..........\...\.......\...\Repository
..........\...\.......\...\Root
..........\...\.......\fifo4.v
..........\...\.......\simple_spi_top.v
..........\sim
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\rtl_sim
..........\...\.......\bin
..........\...\.......\...\CVS
..........\...\.......\...\...\Entries
..........\...\.......\...\...\Repository
..........\...\.......\...\...\Root
..........\...\.......\...\Makefile
..........\...\.......\CVS
..........\...\.......\...\Entries
..........\...\.......\...\Repository
..........\...\.......\...\Root
..........\...\.......\run
..........\...\.......\...\CVS
..........\...\.......\...\...\Entries
..........\...\.......\...\...\Repository
..........\...\.......\...\...\Root
..........\...\.......\...\Makefile
..........\...\.......\...\ncsim.log
..........\...\.......\...\ncvlog.log
..........\...\.......\...\ncwork
..........\...\.......\...\......\cds.lib
..........\...\.......\...\......\CVS
..........\...\.......\...\......\...\Entries
..........\...\.......\...\......\...\Repository
..........\...\.......\...\......\...\Root
..........\...\.......\...\......\hdl.var
..........\...\.......\...\......\work
..........\...\.......\...\......\....\.cdsvmod
..........\...\.......\...\......\....\.inca.db.135.linux
..........\...\.......\...\......\....\.inca.db.148.lnx86
..........\...\.......\...\......\....\CVS
..........\...\.......\...\......\....\...\Entries
..........\...\.......\...\......\....\...\Repository
..........\...\.......\...\......\....\...\Root
..........\...\.......\...\......\....\inca.linux.135.pak
..........\...\.......\...\......\....\inca.lnx86.148.pak
..........\...\.......\...\simvision.sv
..........\...\.......\...\stdout.log
..........\...\.......\...\waves
..........\...\.......\...\.....\CVS
..........\...\.......\...\.....\...\Entries
..........\...\.......\...\.....\...\Repository
..........\...\.......\...\.....\...\Root
..........\...\.......\...\.....\waves.do
..........\bench
..........\.....\CVS
..........\.....\...\Entries
..........\.....\...\Repository
..........\.....\...\Root
..........\.....\verilog
..........\.....\.......\CVS
..........\.....\.......\...\Entries
..........\.....\.......\...\Repository
..........\.....\.......\...\Root
..........\.....\.......\spi_slave_model.v
..........\.....\.......\tst_bench_top.v
..........\.....\.......\wb_master_model.v
..........\CVS
..........\...\Entries
..........\...\Repository
..........\...\Root
..........\doc
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\simple_spi.pdf
..........\...\src
..........\...\...\CVS
..........\...\...\...\Entries
..........\...\...\...\Repository
..........\...\...\...\Root
..........\...\...\simple_spi.doc
..........\rtl
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\verilog
..........\...\.......\CVS
..........\...\.......\...\Entries
..........\...\.......\...\Repository
..........\...\.......\...\Root
..........\...\.......\fifo4.v
..........\...\.......\simple_spi_top.v
..........\sim
..........\...\CVS
..........\...\...\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\rtl_sim
..........\...\.......\bin
..........\...\.......\...\CVS
..........\...\.......\...\...\Entries
..........\...\.......\...\...\Repository
..........\...\.......\...\...\Root
..........\...\.......\...\Makefile
..........\...\.......\CVS
..........\...\.......\...\Entries
..........\...\.......\...\Repository
..........\...\.......\...\Root
..........\...\.......\run
..........\...\.......\...\CVS
..........\...\.......\...\...\Entries
..........\...\.......\...\...\Repository
..........\...\.......\...\...\Root
..........\...\.......\...\Makefile
..........\...\.......\...\ncsim.log
..........\...\.......\...\ncvlog.log
..........\...\.......\...\ncwork
..........\...\.......\...\......\cds.lib
..........\...\.......\...\......\CVS
..........\...\.......\...\......\...\Entries
..........\...\.......\...\......\...\Repository
..........\...\.......\...\......\...\Root
..........\...\.......\...\......\hdl.var
..........\...\.......\...\......\work
..........\...\.......\...\......\....\.cdsvmod
..........\...\.......\...\......\....\.inca.db.135.linux
..........\...\.......\...\......\....\.inca.db.148.lnx86
..........\...\.......\...\......\....\CVS
..........\...\.......\...\......\....\...\Entries
..........\...\.......\...\......\....\...\Repository
..........\...\.......\...\......\....\...\Root
..........\...\.......\...\......\....\inca.linux.135.pak
..........\...\.......\...\......\....\inca.lnx86.148.pak
..........\...\.......\...\simvision.sv
..........\...\.......\...\stdout.log
..........\...\.......\...\waves
..........\...\.......\...\.....\CVS
..........\...\.......\...\.....\...\Entries
..........\...\.......\...\.....\...\Repository
..........\...\.......\...\.....\...\Root
..........\...\.......\...\.....\waves.do