文件名称:half_clk
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用verilog编写适中分频器
并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
并且还有测试程序-verilog prepared with moderate frequency divider and another test procedures
相关搜索： 分频器
(系统自动生成,下载前可以参看下载内容)
下载文件列表
half_clk
........\half_clk.cr.mti
........\half_clk.mpf
........\half_clk.v
........\half_clkt.v
........\transcript
........\vish_stacktrace.vstf
........\vsim.wlf
........\work
........\....\half_clk
........\....\........\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\half_clkt
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\_info
........\half_clk.cr.mti
........\half_clk.mpf
........\half_clk.v
........\half_clkt.v
........\transcript
........\vish_stacktrace.vstf
........\vsim.wlf
........\work
........\....\half_clk
........\....\........\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\half_clkt
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\_info