文件名称:adder215
介绍说明--下载内容均来自于网络,请自行研究使用
有关于加法器的vhdl编程,是用赛灵思的fpga实现的,可以在赛灵思网站上找到更具体的说明-Adder on the vhdl program is the use of the Xilinx fpga achieve. Xilinx website can be found on more specific details of their
(系统自动生成,下载前可以参看下载内容)
下载文件列表
addsub.v
addsub.vhd
comparator.v
comparator.vhd
ldenaddsub.v
ldenaddsub.vhd
magcomp.v
magcomp.vhd
mag_comp_sign.v
nx2mult.v
nx2mult.vhd
readme.txt
twoscomp.v
twoscomp.vhd
addsub.vhd
comparator.v
comparator.vhd
ldenaddsub.v
ldenaddsub.vhd
magcomp.v
magcomp.vhd
mag_comp_sign.v
nx2mult.v
nx2mult.vhd
readme.txt
twoscomp.v
twoscomp.vhd