文件名称:pic16c57code
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 67kb
- 下载次数：
- 0次
- 提 供 者：
- 俞**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
此代码可用modelsim进行仿真，修改rom之后可用quartusII进行综合，希望你们能对此程序不断完善。-modelsim this code can be used for simulation, After amending rom available quartusII comprehensive and hope that you can constantly improve this procedure.
相关搜索： PIC16C57
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test1
.....\alu.v
.....\alu.v.bak
.....\clock.v
.....\encode.v
.....\encode.v.bak
.....\ir.v
.....\ir.v.bak
.....\pc.v
.....\pc.v.bak
.....\ram_sel_wdrd.v
.....\sel_tmp2.v
.....\stack.v
.....\stack.v.bak
.....\test1.cr.mti
.....\test1.mpf
.....\test1_cpu.v
.....\test1_cpu.v.bak
.....\transcript
.....\vish_stacktrace.vstf
.....\vsim.wlf
.....\w.v
.....\w.v.bak
.....\work
.....\....\alu
.....\....\...\verilog.asm
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\clock
.....\....\.....\verilog.asm
.....\....\.....\_primary.dat
.....\....\.....\_primary.vhd
.....\....\encode
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\ir
.....\....\..\verilog.asm
.....\....\..\_primary.dat
.....\....\..\_primary.vhd
.....\....\pc
.....\....\..\verilog.asm
.....\....\..\_primary.dat
.....\....\..\_primary.vhd
.....\....\ram_sel_wdrd
.....\....\............\verilog.asm
.....\....\............\_primary.dat
.....\....\............\_primary.vhd
.....\....\risc_mcu
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\sel_tmp2
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\stack
.....\....\.....\verilog.asm
.....\....\.....\_primary.dat
.....\....\.....\_primary.vhd
.....\....\test1_cpu
.....\....\.........\verilog.asm
.....\....\.........\_primary.dat
.....\....\.........\_primary.vhd
.....\....\w
.....\....\.\verilog.asm
.....\....\.\_primary.dat
.....\....\.\_primary.vhd
.....\....\_info
.....\alu.v
.....\alu.v.bak
.....\clock.v
.....\encode.v
.....\encode.v.bak
.....\ir.v
.....\ir.v.bak
.....\pc.v
.....\pc.v.bak
.....\ram_sel_wdrd.v
.....\sel_tmp2.v
.....\stack.v
.....\stack.v.bak
.....\test1.cr.mti
.....\test1.mpf
.....\test1_cpu.v
.....\test1_cpu.v.bak
.....\transcript
.....\vish_stacktrace.vstf
.....\vsim.wlf
.....\w.v
.....\w.v.bak
.....\work
.....\....\alu
.....\....\...\verilog.asm
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\clock
.....\....\.....\verilog.asm
.....\....\.....\_primary.dat
.....\....\.....\_primary.vhd
.....\....\encode
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\ir
.....\....\..\verilog.asm
.....\....\..\_primary.dat
.....\....\..\_primary.vhd
.....\....\pc
.....\....\..\verilog.asm
.....\....\..\_primary.dat
.....\....\..\_primary.vhd
.....\....\ram_sel_wdrd
.....\....\............\verilog.asm
.....\....\............\_primary.dat
.....\....\............\_primary.vhd
.....\....\risc_mcu
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\sel_tmp2
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\stack
.....\....\.....\verilog.asm
.....\....\.....\_primary.dat
.....\....\.....\_primary.vhd
.....\....\test1_cpu
.....\....\.........\verilog.asm
.....\....\.........\_primary.dat
.....\....\.........\_primary.vhd
.....\....\w
.....\....\.\verilog.asm
.....\....\.\_primary.dat
.....\....\.\_primary.vhd
.....\....\_info