文件名称:16bit_booth_multiplier_STG
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verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
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VHDL
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下载文件列表
Booth_Multiplier_STG.v
Controller.v
Datapath.v
testBench.v
Controller.v
Datapath.v
testBench.v