文件名称:MVHDL
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本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證-the parallel program for controlling flash ROM programs, rom flash can be read out information, After drawing CPLD controller will turn into VESA video signal and output to screen. The program has strong experience card
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MVHDL
.....\am29lv160d.v
.....\init.mem
.....\minipg_tb.cr.mti
.....\minipg_tb.mpf
.....\SystemTB.vhd
.....\vesa_vga_timesim.sdf
.....\vesa_vga_timesim.vhd
.....\vsim.wlf
.....\work
.....\....\@v@i@t@a@lbuf
.....\....\.............\verilog.asm
.....\....\.............\_primary.dat
.....\....\.............\_primary.vhd
.....\....\am29lv160d
.....\....\..........\verilog.asm
.....\....\..........\_primary.dat
.....\....\..........\_primary.vhd
.....\....\systemtb
.....\....\........\systemtb_b.asm
.....\....\........\systemtb_b.dat
.....\....\........\_primary.dat
.....\....\vesa_vga
.....\....\........\structure.asm
.....\....\........\structure.dat
.....\....\........\vesa_vga.asm
.....\....\........\vesa_vga.dat
.....\....\........\vesa_vga_bh.asm
.....\....\........\vesa_vga_bh.dat
.....\....\........\_primary.dat
.....\....\_info
.....\am29lv160d.v
.....\init.mem
.....\minipg_tb.cr.mti
.....\minipg_tb.mpf
.....\SystemTB.vhd
.....\vesa_vga_timesim.sdf
.....\vesa_vga_timesim.vhd
.....\vsim.wlf
.....\work
.....\....\@v@i@t@a@lbuf
.....\....\.............\verilog.asm
.....\....\.............\_primary.dat
.....\....\.............\_primary.vhd
.....\....\am29lv160d
.....\....\..........\verilog.asm
.....\....\..........\_primary.dat
.....\....\..........\_primary.vhd
.....\....\systemtb
.....\....\........\systemtb_b.asm
.....\....\........\systemtb_b.dat
.....\....\........\_primary.dat
.....\....\vesa_vga
.....\....\........\structure.asm
.....\....\........\structure.dat
.....\....\........\vesa_vga.asm
.....\....\........\vesa_vga.dat
.....\....\........\vesa_vga_bh.asm
.....\....\........\vesa_vga_bh.dat
.....\....\........\_primary.dat
.....\....\_info