文件名称:adder_ahead8bit
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本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
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下载文件列表
adder_ahead8bit
...............\adder_ahead8bit.cr.mti
...............\adder_ahead8bit.mpf
...............\adder_ahead8bit.v
...............\transcript
...............\work
...............\....\add_ahead
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\_info
...............\adder_ahead8bit.cr.mti
...............\adder_ahead8bit.mpf
...............\adder_ahead8bit.v
...............\transcript
...............\work
...............\....\add_ahead
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\_info