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文件名称:CALCULAT.ZIP

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 609kb
  • 下载次数：
  • 0次
  • 提 供 者：
  • 沈**
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ALDEC.INI

ALDEC.LOG

BTI.INI

CALCULAT

........\ADDER.ALR

........\ADDER.ASX

........\ADDER.BAK

........\ADDER.EDF

........\ADDER.ER

........\ADDER.LOG

........\ADDER.OPT

........\ADDER.V

........\CALCULA1.BSC

........\CALCULA1.ERR

........\CALCULA1.SCH

........\CALCULAT.ALB

........\CALCULAT.BIT

........\CALCULAT.EDN

........\CALCULAT.LL

........\CALCULAT.PRJ

........\CALCULAT.TVE

........\CALCULAT.UCF

........\DECODER10TO7.ALR

........\DECODER10TO7.ASX

........\DECODER10TO7.EDF

........\DECODER10TO7.ER

........\DECODER10TO7.LOG

........\DECODER10TO7.OPT

........\DECODER10TO7.V

........\DPMCOMP.TMP

........\...........\CHIPS

........\...........\.....\ADDER

........\...........\.....\.....\ADDER.CST

........\...........\.....\.....\ADDER.RPT

........\...........\.....\.....\ADDER.WS

........\...........\.....\ADDER_OPT

........\...........\.....\.........\ADDER_OPT.CST

........\...........\.....\.........\ADDER_OPT.RPT

........\...........\.....\.........\ADDER_OPT.WS

........\...........\.....\DECODER10TO7

........\...........\.....\............\DECODER10TO7.CST

........\...........\.....\............\DECODER10TO7.RPT

........\...........\.....\............\DECODER10TO7.WS

........\...........\.....\DECODER10TO7_OPT

........\...........\.....\................\DECODER10TO7_OPT.CST

........\...........\.....\................\DECODER10TO7_OPT.RPT

........\...........\.....\................\DECODER10TO7_OPT.WS

........\...........\.....\FREQDIVIDE

........\...........\.....\..........\FREQDIVIDE.CST

........\...........\.....\..........\FREQDIVIDE.RPT

........\...........\.....\..........\FREQDIVIDE.WS

........\...........\.....\FREQDIVIDE_OPT

........\...........\.....\..............\FREQDIVIDE_OPT.CST

........\...........\.....\..............\FREQDIVIDE_OPT.RPT

........\...........\.....\..............\FREQDIVIDE_OPT.WS

........\...........\.....\MERGE

........\...........\.....\.....\MERGE.CST

........\...........\.....\.....\MERGE.RPT

........\...........\.....\.....\MERGE.WS

........\...........\.....\MERGE_OPT

........\...........\.....\.........\MERGE_OPT.CST

........\...........\.....\.........\MERGE_OPT.RPT

........\...........\.....\.........\MERGE_OPT.WS

........\...........\.....\SCAN

........\...........\.....\....\SCAN.CST

........\...........\.....\....\SCAN.RPT

........\...........\.....\....\SCAN.WS

........\...........\.....\SCAN_OPT

........\...........\.....\........\SCAN_OPT.CST

........\...........\.....\........\SCAN_OPT.RPT

........\...........\.....\........\SCAN_OPT.WS

........\...........\.....\SELECTOR

........\...........\.....\........\SELECTOR.CST

........\...........\.....\........\SELECTOR.RPT

........\...........\.....\........\SELECTOR.WS

........\...........\.....\SELECTOR_OPT

........\...........\.....\............\SELECTOR_OPT.CST

........\...........\.....\............\SELECTOR_OPT.RPT

........\...........\.....\............\SELECTOR_OPT.WS

........\...........\WORKDIRS

........\...........\........\WORK

........\...........\........\....\ADDER%VERILOG.SYN

........\...........\........\....\ADDER%VERILOG__VERILOG.SYN

........\...........\........\....\ADDER.HNL

........\...........\........\....\ADDER.MRA

........\...........\........\....\ADDER.OUT

........\...........\........\....\ADDER.STS

........\...........\........\....\ANAL.INFO

........\...........\........\....\ANAL.OUT

........\...........\........\....\DECODER10TO7%VERILOG.SYN

........\...........\........\....\DECODER10TO7%VERILOG__VERILOG.SYN

........\...........\........\....\DECODER10TO7.HNL

........\...........\........\....\DECODER10TO7.MRA

........\...........\........\....\DECODER10TO7.OUT

........\...........\........\....\DECODER10TO7.STS

........\...........\........\....\FREQDIVIDE%VERILOG.SYN

........\...........\........\....\FREQDIVIDE%VERILOG__VERILOG.SYN

........\...........\........\....\FREQDIVIDE.HNL

........\...........\........\....\FREQDIVIDE.MRA

........\...........\........\....\FREQDIVIDE.OUT

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