文件名称:MCU-counter
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 730kb
- 下载次数：
- 0次
- 提 供 者：
- u**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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下载文件列表
MCU-counter
...........\doc
...........\...\设计说明.doc
...........\modelsim
...........\........\counter
...........\........\.......\control0
...........\........\.......\........\verilog.asm
...........\........\.......\........\_primary.dat
...........\........\.......\........\_primary.vhd
...........\........\.......\count_all
...........\........\.......\.........\verilog.asm
...........\........\.......\.........\_primary.dat
...........\........\.......\.........\_primary.vhd
...........\........\.......\data0
...........\........\.......\.....\verilog.asm
...........\........\.......\.....\_primary.dat
...........\........\.......\.....\_primary.vhd
...........\........\.......\founction1
...........\........\.......\..........\verilog.asm
...........\........\.......\..........\_primary.dat
...........\........\.......\..........\_primary.vhd
...........\........\.......\test
...........\........\.......\....\verilog.asm
...........\........\.......\....\_primary.dat
...........\........\.......\....\_primary.vhd
...........\........\.......\_info
...........\........\counter.cr.mti
...........\........\counter.mpf
...........\........\transcript
...........\........\vsim.wlf
...........\........\work
...........\........\....\control0
...........\........\....\........\verilog.asm
...........\........\....\........\_primary.dat
...........\........\....\........\_primary.vhd
...........\........\....\control1
...........\........\....\........\verilog.asm
...........\........\....\........\_primary.dat
...........\........\....\........\_primary.vhd
...........\........\....\counter
...........\........\....\.......\verilog.asm
...........\........\....\.......\_primary.dat
...........\........\....\.......\_primary.vhd
...........\........\....\count_all
...........\........\....\.........\verilog.asm
...........\........\....\.........\_primary.dat
...........\........\....\.........\_primary.vhd
...........\........\....\data0
...........\........\....\.....\verilog.asm
...........\........\....\.....\_primary.dat
...........\........\....\.....\_primary.vhd
...........\........\....\data1
...........\........\....\.....\verilog.asm
...........\........\....\.....\_primary.dat
...........\........\....\.....\_primary.vhd
...........\........\....\test
...........\........\....\....\verilog.asm
...........\........\....\....\_primary.dat
...........\........\....\....\_primary.vhd
...........\........\....\testbench
...........\........\....\.........\verilog.asm
...........\........\....\.........\_primary.dat
...........\........\....\.........\_primary.vhd
...........\........\....\_info
...........\........\备注.doc
...........\project
...........\.......\control0.bsf
...........\.......\control1.bsf
...........\.......\counter.asm.rpt
...........\.......\counter.bdf
...........\.......\counter.bsf
...........\.......\counter.cdf
...........\.......\counter.done
...........\.......\counter.eda.rpt
...........\.......\counter.fit.rpt
...........\.......\counter.fit.smsg
...........\.......\counter.fit.summary
...........\.......\counter.flow.rpt
...........\.......\counter.map.rpt
...........\.......\counter.map.smsg
...........\.......\counter.map.summary
...........\.......\counter.pin
...........\.......\counter.pof
...........\.......\counter.qpf
...........\.......\counter.qsf
...........\.......\counter.qws
...........\.......\counter.sim.rpt
...........\.......\counter.sof
...........\.......\counter.tan.rpt
...........\.......\counter.tan.summary
...........\.......\counter.v
...........\.......\counter.vwf
...........\.......\count_all.bsf
...........\.......\data0.bsf
...........\.......\data1.bsf
...........\.......\db
...........\.......\..\altsyncram_fgi2.tdf
...........\.......\..\altsyncram_hgi2.tdf
...........\.......\..\altsyncram_jgi2.tdf
...........\.......\..\altsyncram_jji2.tdf
...........\doc
...........\...\设计说明.doc
...........\modelsim
...........\........\counter
...........\........\.......\control0
...........\........\.......\........\verilog.asm
...........\........\.......\........\_primary.dat
...........\........\.......\........\_primary.vhd
...........\........\.......\count_all
...........\........\.......\.........\verilog.asm
...........\........\.......\.........\_primary.dat
...........\........\.......\.........\_primary.vhd
...........\........\.......\data0
...........\........\.......\.....\verilog.asm
...........\........\.......\.....\_primary.dat
...........\........\.......\.....\_primary.vhd
...........\........\.......\founction1
...........\........\.......\..........\verilog.asm
...........\........\.......\..........\_primary.dat
...........\........\.......\..........\_primary.vhd
...........\........\.......\test
...........\........\.......\....\verilog.asm
...........\........\.......\....\_primary.dat
...........\........\.......\....\_primary.vhd
...........\........\.......\_info
...........\........\counter.cr.mti
...........\........\counter.mpf
...........\........\transcript
...........\........\vsim.wlf
...........\........\work
...........\........\....\control0
...........\........\....\........\verilog.asm
...........\........\....\........\_primary.dat
...........\........\....\........\_primary.vhd
...........\........\....\control1
...........\........\....\........\verilog.asm
...........\........\....\........\_primary.dat
...........\........\....\........\_primary.vhd
...........\........\....\counter
...........\........\....\.......\verilog.asm
...........\........\....\.......\_primary.dat
...........\........\....\.......\_primary.vhd
...........\........\....\count_all
...........\........\....\.........\verilog.asm
...........\........\....\.........\_primary.dat
...........\........\....\.........\_primary.vhd
...........\........\....\data0
...........\........\....\.....\verilog.asm
...........\........\....\.....\_primary.dat
...........\........\....\.....\_primary.vhd
...........\........\....\data1
...........\........\....\.....\verilog.asm
...........\........\....\.....\_primary.dat
...........\........\....\.....\_primary.vhd
...........\........\....\test
...........\........\....\....\verilog.asm
...........\........\....\....\_primary.dat
...........\........\....\....\_primary.vhd
...........\........\....\testbench
...........\........\....\.........\verilog.asm
...........\........\....\.........\_primary.dat
...........\........\....\.........\_primary.vhd
...........\........\....\_info
...........\........\备注.doc
...........\project
...........\.......\control0.bsf
...........\.......\control1.bsf
...........\.......\counter.asm.rpt
...........\.......\counter.bdf
...........\.......\counter.bsf
...........\.......\counter.cdf
...........\.......\counter.done
...........\.......\counter.eda.rpt
...........\.......\counter.fit.rpt
...........\.......\counter.fit.smsg
...........\.......\counter.fit.summary
...........\.......\counter.flow.rpt
...........\.......\counter.map.rpt
...........\.......\counter.map.smsg
...........\.......\counter.map.summary
...........\.......\counter.pin
...........\.......\counter.pof
...........\.......\counter.qpf
...........\.......\counter.qsf
...........\.......\counter.qws
...........\.......\counter.sim.rpt
...........\.......\counter.sof
...........\.......\counter.tan.rpt
...........\.......\counter.tan.summary
...........\.......\counter.v
...........\.......\counter.vwf
...........\.......\count_all.bsf
...........\.......\data0.bsf
...........\.......\data1.bsf
...........\.......\db
...........\.......\..\altsyncram_fgi2.tdf
...........\.......\..\altsyncram_hgi2.tdf
...........\.......\..\altsyncram_jgi2.tdf
...........\.......\..\altsyncram_jji2.tdf