文件名称:aes_core
介绍说明－－下载内容均来自于网络，请自行研究使用
AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
相关搜索： AES
verilog
aes
verilog
VERILOG
CODE
FOR
AES
ALGORITHM
aes
verilog
code
Verilog
AES
aes_core
tar
aes
core
aes_core
加密
verilog
verilog
aes
verilog
VERILOG
CODE
FOR
AES
ALGORITHM
aes
verilog
code
Verilog
AES
aes_core
tar
aes
core
aes_core
加密
verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
aes_core
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Repository
........\.....\...\Root
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\test_bench_top.v
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\doc
........\...\aes.pdf
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\verilog
........\...\.......\aes_cipher_top.v
........\...\.......\aes_inv_cipher_top.v
........\...\.......\aes_inv_sbox.v
........\...\.......\aes_key_expand_128.v
........\...\.......\aes_rcon.v
........\...\.......\aes_sbox.v
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\timescale.v
........\sim
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\rtl_sim
........\...\.......\bin
........\...\.......\...\CVS
........\...\.......\...\...\Entries
........\...\.......\...\...\Repository
........\...\.......\...\...\Root
........\...\.......\...\Makefile
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\run
........\...\.......\...\CVS
........\...\.......\...\...\Entries
........\...\.......\...\...\Repository
........\...\.......\...\...\Root
........\...\.......\...\waves
........\...\.......\...\.....\CVS
........\...\.......\...\.....\...\Entries
........\...\.......\...\.....\...\Repository
........\...\.......\...\.....\...\Root
........\...\.......\...\.....\waves.do
........\syn
........\...\bin
........\...\...\comp.dc
........\...\...\CVS
........\...\...\...\Entries
........\...\...\...\Repository
........\...\...\...\Root
........\...\...\design_spec.dc
........\...\...\lib_spec.dc
........\...\...\read.dc
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\vim_session.vim
........\bench
........\.....\CVS
........\.....\...\Entries
........\.....\...\Repository
........\.....\...\Root
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\...\Entries
........\.....\.......\...\Repository
........\.....\.......\...\Root
........\.....\.......\test_bench_top.v
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\doc
........\...\aes.pdf
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\rtl
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\verilog
........\...\.......\aes_cipher_top.v
........\...\.......\aes_inv_cipher_top.v
........\...\.......\aes_inv_sbox.v
........\...\.......\aes_key_expand_128.v
........\...\.......\aes_rcon.v
........\...\.......\aes_sbox.v
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\timescale.v
........\sim
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\...\rtl_sim
........\...\.......\bin
........\...\.......\...\CVS
........\...\.......\...\...\Entries
........\...\.......\...\...\Repository
........\...\.......\...\...\Root
........\...\.......\...\Makefile
........\...\.......\CVS
........\...\.......\...\Entries
........\...\.......\...\Repository
........\...\.......\...\Root
........\...\.......\run
........\...\.......\...\CVS
........\...\.......\...\...\Entries
........\...\.......\...\...\Repository
........\...\.......\...\...\Root
........\...\.......\...\waves
........\...\.......\...\.....\CVS
........\...\.......\...\.....\...\Entries
........\...\.......\...\.....\...\Repository
........\...\.......\...\.....\...\Root
........\...\.......\...\.....\waves.do
........\syn
........\...\bin
........\...\...\comp.dc
........\...\...\CVS
........\...\...\...\Entries
........\...\...\...\Repository
........\...\...\...\Root
........\...\...\design_spec.dc
........\...\...\lib_spec.dc
........\...\...\read.dc
........\...\CVS
........\...\...\Entries
........\...\...\Repository
........\...\...\Root
........\vim_session.vim