文件名称:Comparators_16B
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verilog 实现 优化的16位比较器 可以输出大于，小于，等于。模块化设计，可扩展为32位-Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32
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Comparators_16B
...............\com.v
...............\comparators.cr.mti
...............\comparators.mpf
...............\testbanche.v
...............\transcript
...............\vsim.wlf
...............\work
...............\....\@c@o@m@p1
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@o@m@p16
...............\....\..........\verilog.asm
...............\....\..........\_primary.dat
...............\....\..........\_primary.vhd
...............\....\@c@o@m@p2
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@o@m@p4
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@o@m@p8
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@t@r@l
...............\....\........\verilog.asm
...............\....\........\_primary.dat
...............\....\........\_primary.vhd
...............\....\@l@e@v@e@l
...............\....\..........\verilog.asm
...............\....\..........\_primary.dat
...............\....\..........\_primary.vhd
...............\....\com
...............\....\...\verilog.asm
...............\....\...\_primary.dat
...............\....\...\_primary.vhd
...............\....\testbanch
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\_info
...............\com.v
...............\comparators.cr.mti
...............\comparators.mpf
...............\testbanche.v
...............\transcript
...............\vsim.wlf
...............\work
...............\....\@c@o@m@p1
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@o@m@p16
...............\....\..........\verilog.asm
...............\....\..........\_primary.dat
...............\....\..........\_primary.vhd
...............\....\@c@o@m@p2
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@o@m@p4
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@o@m@p8
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\@c@t@r@l
...............\....\........\verilog.asm
...............\....\........\_primary.dat
...............\....\........\_primary.vhd
...............\....\@l@e@v@e@l
...............\....\..........\verilog.asm
...............\....\..........\_primary.dat
...............\....\..........\_primary.vhd
...............\....\com
...............\....\...\verilog.asm
...............\....\...\_primary.dat
...............\....\...\_primary.vhd
...............\....\testbanch
...............\....\.........\verilog.asm
...............\....\.........\_primary.dat
...............\....\.........\_primary.vhd
...............\....\_info