文件名称:cal_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
计算器芯片的verilog实现代码！
时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cal
...\alu.v
...\apportionment.v
...\apportionment.v.bak
...\datareg.v
...\display.v
...\display_control.v
...\encode.v
...\encode.v.bak
...\ireg.v
...\sicense.v
...\alu.v
...\apportionment.v
...\apportionment.v.bak
...\datareg.v
...\display.v
...\display_control.v
...\encode.v
...\encode.v.bak
...\ireg.v
...\sicense.v