The basic parts of the BFSK transmitter are the preamble and the data input circuit. The preamble sequence is positioned in front of each packet of 122 bits for a total of 128 bits packet. The main purpose of the preamble is to facilitate the reception, providing both bit and packet synchronization. The data input circuit mainly consists from memory elements and a convolutional encoder with r=1/2. Thus, the input bits must be stored in a temporary memory and be partitioned in blocks of 61 bits. Then the convolutional encoder doubles the bits and adds two more trail bits at the end of the message. A multiplexer makes sure that that the correct sequence, choosing between preamble and encoded bit, is propagating to the next stage. The next stage of the transmitter consists of two direct digital synthesizers (DDS), and a multiplexer that is fed with zeros and ones to choose between the two frequencies. For each bit, we allow 64 samples of the respective frequency to be transmitted. Although the implementation of the selection between the two frequencies is strait forward, the enable port of the multiplexer should be used along with a Matlab Code (MCode) block in order to prevent the propagation of some initial undefined states during initialization. The only functionality of the MCode block is to enable the multiplexer after the first bit of the preamble is detected. Finally, pulse shaping is not used and the addition of a single filter after the last multiplexer would suffice to implement this functionality.