文件名称:I2C_verilog

  • 所属分类:
  • 其它资源
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2008-10-13
  • 文件大小:
  • 510.51kb
  • 下载次数:
  • 1次
  • 提 供 者:
  • 郑*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用verilog设计了一个简洁而实用的I2C总线控制器,对大家学习FPGA和I2C总线接口等相关方面的知识有较大的帮助。
(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : 1985542i2c_verilog.rar 列表
I2C总线VHDL-Verilog+HDL源码\i2c\bench\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\bench\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\bench\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\i2c_slave_model.v
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\spi_slave_model.v
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\tst_bench_top.v
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\wb_master_model.v
I2C总线VHDL-Verilog+HDL源码\i2c\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\doc\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\doc\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\doc\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\doc\i2c_specs.pdf
I2C总线VHDL-Verilog+HDL源码\i2c\doc\src\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\doc\src\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\doc\src\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\doc\src\I2C_specs.doc
I2C总线VHDL-Verilog+HDL源码\i2c\documentation\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\documentation\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\documentation\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\i2c_master_bit_ctrl.v
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\i2c_master_byte_ctrl.v
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\i2c_master_defines.v
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\i2c_master_top.v
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\timescale.v
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\I2C.VHD
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\i2c_master_bit_ctrl.vhd
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\i2c_master_byte_ctrl.vhd
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\i2c_master_top.vhd
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\readme
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\tst_ds1621.vhd
I2C总线VHDL-Verilog+HDL源码\i2c\sim\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\sim\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\sim\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\bench.vcd
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\INCA_libs\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\INCA_libs\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\INCA_libs\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\ncverilog.key
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\ncverilog.log
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\run
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\waves\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\waves\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\waves\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\software\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\software\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\software\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\software\drivers\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\software\drivers\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\software\drivers\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\software\include\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\software\include\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\software\include\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\software\include\oc_i2c_master.h
I2C总线VHDL-Verilog+HDL源码\i2c\verilog\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\verilog\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\verilog\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\vhdl\CVS\Entries
I2C总线VHDL-Verilog+HDL源码\i2c\vhdl\CVS\Repository
I2C总线VHDL-Verilog+HDL源码\i2c\vhdl\CVS\Root
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\INCA_libs\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\waves\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\INCA_libs
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run\waves
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\doc\src\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog\run
I2C总线VHDL-Verilog+HDL源码\i2c\software\drivers\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\software\include\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\bench\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\bench\verilog
I2C总线VHDL-Verilog+HDL源码\i2c\doc\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\doc\src
I2C总线VHDL-Verilog+HDL源码\i2c\documentation\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\verilog
I2C总线VHDL-Verilog+HDL源码\i2c\rtl\vhdl
I2C总线VHDL-Verilog+HDL源码\i2c\sim\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\sim\i2c_verilog
I2C总线VHDL-Verilog+HDL源码\i2c\software\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\software\drivers
I2C总线VHDL-Verilog+HDL源码\i2c\software\include
I2C总线VHDL-Verilog+HDL源码\i2c\verilog\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\vhdl\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\bench
I2C总线VHDL-Verilog+HDL源码\i2c\CVS
I2C总线VHDL-Verilog+HDL源码\i2c\doc
I2C总线VHDL-Verilog+HDL源码\i2c\documentation
I2C总线VHDL-Verilog+HDL源码\i2c\rtl
I2C总线VHDL-Verilog+HDL源码\i2c\sim
I2C总线VHDL-Verilog+HDL源码\i2c\software
I2C总线VHDL-Verilog+HDL源码\i2c\verilog
I2C总线VHDL-Verilog+HDL源码\i2c\vhdl
I2C总线VHDL-Verilog+HDL源码\i2c
I2C总线VHDL-Verilog+HDL源码

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