文件名称:100vhdl
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VHDL源代码100例(1)自带目录!请仔细查看!
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压缩包 : 19854777100vhdl.rar 列表 1_ADDER\1_ADDER\1_ADDER.exp 1_ADDER\1_ADDER\files\L1.rpt 1_ADDER\1_ADDER\files\L2.rpt 1_ADDER\1_ADDER\files\L3.rpt 1_ADDER\1_ADDER\workdirs\aa\ADDER.sim 1_ADDER\1_ADDER\workdirs\aa\ADDER.syn 1_ADDER\1_ADDER\workdirs\aa\Anal.info 1_ADDER\1_ADDER\workdirs\aa\Anal.out 1_ADDER\1_ADDER\workdirs\WORK\Anal.info 1_ADDER\1_ADDER\workdirs\WORK\Anal.out 1_ADDER\1_ADDER\workdirs\WORK\BIT_RTL_ADDER.sim 1_ADDER\1_ADDER\workdirs\WORK\BIT_RTL_ADDER.syn 1_ADDER\1_adder.acf 1_ADDER\1_adder.hif 1_ADDER\1_adder.mmf 1_ADDER\1_ADDER.VHD 1_ADDER\bir_rtl_adder.acf 1_ADDER\bir_rtl_adder.hif 1_ADDER\bir_rtl_adder.mmf 1_ADDER\bir_rtl_adder.tdf 1_ADDER\bit_rtl_adder.acf 1_ADDER\bit_rtl_adder.hif 1_ADDER\bit_rtl_adder.mmf 1_ADDER\bit_rtl_adder.vhd 1_ADDER\LIB.DLS 1_ADDER\README.TXT 1_ADDER\U2268397.DLS 2_ADDER\2_ADDER.VHD 2_ADDER\README.TXT 3_MUL\3_MUL.VHD 3_MUL\README.TXT 4_COMP\4_COMP.VHD 4_COMP\README.TXT 5_MUX2\5_MUX2.VHD 5_MUX2\README.TXT 6_REG\6_REG.VHD 6_REG\README.TXT 7_shiftreg\7_MVL7_functions.vhd 7_shiftreg\7_shiftreg.vhd 7_shiftreg\7_synthesis_types.vhd 7_shiftreg\7_test_vector.vhd 7_shiftreg\7_TYPES.VHD 7_shiftreg\README.TXT 8_BITPKG\8_BITPKG.VHD 8_BITPKG\8_bit_rtl_lib.vhd 8_BITPKG\README.TXT 9_MVL7_TYPES\9_MVL7_types.vhd 9_MVL7_TYPES\README.TXT 10_function\10_bit_to_int.vhd 10_function\README.TXT 11_wiredor\11_wiredor.vhd 11_wiredor\README.TXT 12_convert\12_convert.vhd 12_convert\README.TXT 13_SHL\13_SHL.VHD 13_SHL\README.TXT 14_MVL7_functions\14_MVL7_functions.vhd 14_MVL7_functions\README.TXT 15_MUX41\15_MUX41.VHD 15_MUX41\15_MVL7_functions.vhd 15_MUX41\15_MVL7_syn_types.vhd 15_MUX41\15_test_vectors_mux41.vhd 15_MUX41\15_TYPES.VHD 15_MUX41\README.TXT 16_MUX\16_multiple_mux.vhd 16_MUX\16_MVL7_functions.vhd 16_MUX\16_test_vectors.vhd 16_MUX\16_TYPES.VHD 16_MUX\README.TXT 16_MUX\TYPES.VHD 17_parity\17_parity.vhd 17_parity\17_test_bench.vhd 17_parity\README.TXT 18_LIB\18_tech_lib.vhd 18_LIB\18_test_lib.vhd 18_LIB\README.TXT 19_test_194\19_test_194.vhd 20_test_159\20_test_159.vhd 21_test_13a\21_test_13a.vhd 1_ADDER\1_ADDER\workdirs\aa 1_ADDER\1_ADDER\workdirs\WORK 1_ADDER\1_ADDER\files 1_ADDER\1_ADDER\workdirs 1_ADDER\1_ADDER 1_ADDER 2_ADDER 3_MUL 4_COMP 5_MUX2 6_REG 7_shiftreg 8_BITPKG 9_MVL7_TYPES 10_function 11_wiredor 12_convert 13_SHL 14_MVL7_functions 15_MUX41 16_MUX 17_parity 18_LIB 19_test_194 20_test_159 21_test_13a 22_deadlock\22_deadlock.vhd 23_test_120\23_Test_120.vhd 24_test_195\24_test_195.vhd 25_test_1\25_test_1.vhd 25_test_1\25_test_1a.vhd 26_test_74s\26_test_74s.vhd 27_test_16\27_test_16.vhd 28_test_64a\28_Test_64a.vhd 29_test_35\29_Test_35.vhd 30_test_3\30_Test_3.vhd 31_test_35b\31_test_35b.vhd 32_test_110b\32_test_110b.vhd 33_comparer\33_COMP.VHD 33_comparer\33_comparer.vhd 33_comparer\33_SIMU.VHD 33_comparer\README.TXT 34_BUS\34_readwrite.VHD 34_BUS\34_readwrite_stim.vhd 34_BUS\README.TXT 35_486_bus\35_486_bus.vhd 35_486_bus\35_486_sys.vhd 35_486_bus\35_bit_pack.vhd 35_486_bus\35_bus_test.vhd 35_486_bus\35_ram_controller.vhd 35_486_bus\75_RAM.VHD 35_486_bus\README.TXT 36_GCD\36_GCD.VHD 36_GCD\36_TEST.VHD 36_GCD\README.TXT 37_test_105\37_test_105.vhd 38_test_28\38_Test_28.vhd 39_wst0dp\39_wst0dp.vhd 39_wst0dp\README.TXT 40_generic_dec\40_generic_dec.vhd 40_generic_dec\README.TXT 41_generic_testbench\40_generic_dec.vhd 41_generic_testbench\41_generic_testbench.vhd 41_generic_testbench\README.TXT 42_MIX\42_MIX.VHD 42_MIX\README.TXT 22_deadlock 23_test_120 24_test_195 25_test_1 26_test_74s 27_test_16 28_test_64a 29_test_35 30_test_3 31_test_35b 32_test_110b 33_comparer 34_BUS 35_486_bus 36_GCD 37_test_105 38_test_28 39_wst0dp 40_generic_dec 41_generic_testbench 42_MIX