文件名称:VerilogHDL_alarmclock
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采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置，源代码对FPGA和CPLD学习者价值很高，
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压缩包 : 61549812veriloghdl_alarmclock.rar 列表 VerilogHDL_alarmclock\alarmclock\alarmclock.asm.rpt VerilogHDL_alarmclock\alarmclock\alarmclock.bsf VerilogHDL_alarmclock\alarmclock\alarmclock.done VerilogHDL_alarmclock\alarmclock\alarmclock.fit.eqn VerilogHDL_alarmclock\alarmclock\alarmclock.fit.rpt VerilogHDL_alarmclock\alarmclock\alarmclock.fit.summary VerilogHDL_alarmclock\alarmclock\alarmclock.flow.rpt VerilogHDL_alarmclock\alarmclock\alarmclock.map.eqn VerilogHDL_alarmclock\alarmclock\alarmclock.map.rpt VerilogHDL_alarmclock\alarmclock\alarmclock.map.summary VerilogHDL_alarmclock\alarmclock\alarmclock.pin VerilogHDL_alarmclock\alarmclock\alarmclock.pof VerilogHDL_alarmclock\alarmclock\alarmclock.qpf VerilogHDL_alarmclock\alarmclock\alarmclock.qsf VerilogHDL_alarmclock\alarmclock\alarmclock.qws VerilogHDL_alarmclock\alarmclock\alarmclock.sim.rpt VerilogHDL_alarmclock\alarmclock\alarmclock.tan.rpt VerilogHDL_alarmclock\alarmclock\alarmclock.tan.summary VerilogHDL_alarmclock\alarmclock\alarmclock.v VerilogHDL_alarmclock\alarmclock\alarmclock.vwf VerilogHDL_alarmclock\alarmclock\cmp_state.ini VerilogHDL_alarmclock\alarmclock\db\alarmclock.(0).cnf.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.(0).cnf.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.(1).cnf.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.(1).cnf.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.asm.qmsg VerilogHDL_alarmclock\alarmclock\db\alarmclock.cmp.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.cmp.ddb VerilogHDL_alarmclock\alarmclock\db\alarmclock.cmp.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.cmp.rdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.cmp.tdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.cmp0.ddb VerilogHDL_alarmclock\alarmclock\db\alarmclock.db_info VerilogHDL_alarmclock\alarmclock\db\alarmclock.eco.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.eds_overflow VerilogHDL_alarmclock\alarmclock\db\alarmclock.fit.qmsg VerilogHDL_alarmclock\alarmclock\db\alarmclock.hier_info VerilogHDL_alarmclock\alarmclock\db\alarmclock.hif VerilogHDL_alarmclock\alarmclock\db\alarmclock.map.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.map.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.map.qmsg VerilogHDL_alarmclock\alarmclock\db\alarmclock.pre_map.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.pre_map.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.psp VerilogHDL_alarmclock\alarmclock\db\alarmclock.rtlv.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.rtlv_sg.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.rtlv_sg_swap.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.sgdiff.cdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.sgdiff.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.sim.hdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.sim.qmsg VerilogHDL_alarmclock\alarmclock\db\alarmclock.sim.rdb VerilogHDL_alarmclock\alarmclock\db\alarmclock.sim.vwf VerilogHDL_alarmclock\alarmclock\db\alarmclock.sld_design_entry.sci VerilogHDL_alarmclock\alarmclock\db\alarmclock.sld_design_entry_dsc.sci VerilogHDL_alarmclock\alarmclock\db\alarmclock.syn_hier_info VerilogHDL_alarmclock\alarmclock\db\alarmclock.tan.qmsg VerilogHDL_alarmclock\alarmclock\db\alarmclock_cmp.qrpt VerilogHDL_alarmclock\alarmclock\db\alarmclock_sim.qrpt VerilogHDL_alarmclock\date\autodate\autodate.asm.rpt VerilogHDL_alarmclock\date\autodate\autodate.bsf VerilogHDL_alarmclock\date\autodate\autodate.done VerilogHDL_alarmclock\date\autodate\autodate.fit.eqn VerilogHDL_alarmclock\date\autodate\autodate.fit.rpt VerilogHDL_alarmclock\date\autodate\autodate.fit.summary VerilogHDL_alarmclock\date\autodate\autodate.flow.rpt VerilogHDL_alarmclock\date\autodate\autodate.map.eqn VerilogHDL_alarmclock\date\autodate\autodate.map.rpt VerilogHDL_alarmclock\date\autodate\autodate.map.summary VerilogHDL_alarmclock\date\autodate\autodate.pin VerilogHDL_alarmclock\date\autodate\autodate.pof VerilogHDL_alarmclock\date\autodate\autodate.qpf VerilogHDL_alarmclock\date\autodate\autodate.qsf VerilogHDL_alarmclock\date\autodate\autodate.qws VerilogHDL_alarmclock\date\autodate\autodate.sim.rpt VerilogHDL_alarmclock\date\autodate\autodate.tan.rpt VerilogHDL_alarmclock\date\autodate\autodate.tan.summary VerilogHDL_alarmclock\date\autodate\autodate.v VerilogHDL_alarmclock\date\autodate\autodate.vwf VerilogHDL_alarmclock\date\autodate\cmp_state.ini VerilogHDL_alarmclock\date\autodate\db\autodate.(0).cnf.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.(0).cnf.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.(1).cnf.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.(1).cnf.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.asm.qmsg VerilogHDL_alarmclock\date\autodate\db\autodate.cmp.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.cmp.ddb VerilogHDL_alarmclock\date\autodate\db\autodate.cmp.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.cmp.rdb VerilogHDL_alarmclock\date\autodate\db\autodate.cmp.tdb VerilogHDL_alarmclock\date\autodate\db\autodate.cmp0.ddb VerilogHDL_alarmclock\date\autodate\db\autodate.db_info VerilogHDL_alarmclock\date\autodate\db\autodate.eco.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.eds_overflow VerilogHDL_alarmclock\date\autodate\db\autodate.fit.qmsg VerilogHDL_alarmclock\date\autodate\db\autodate.hier_info VerilogHDL_alarmclock\date\autodate\db\autodate.hif VerilogHDL_alarmclock\date\autodate\db\autodate.map.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.map.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.map.qmsg VerilogHDL_alarmclock\date\autodate\db\autodate.pre_map.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.pre_map.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.psp VerilogHDL_alarmclock\date\autodate\db\autodate.rtlv.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.rtlv_sg.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.rtlv_sg_swap.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.sgdiff.cdb VerilogHDL_alarmclock\date\autodate\db\autodate.sgdiff.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.sim.hdb VerilogHDL_alarmclock\date\autodate\db\autodate.sim.qmsg VerilogHDL_alarmclock\date\autodate\db\autodate.sim.rdb VerilogHDL_alarmclock\date\autodate\db\autodate.sim.vwf VerilogHDL_alarmclock\date\autodate\db\autodate.sld_design_entry.sci VerilogHDL_alarmclock\date\autodate\db\autodate.sld_design_entry_dsc.sci VerilogHDL_alarmclock\date\autodate\db\autodate.syn_hier_info VerilogHDL_alarmclock\date\autodate\db\autodate.tan.qmsg VerilogHDL_alarmclock\date\autodate\db\autodate_cmp.qrpt VerilogHDL_alarmclock\date\autodate\db\autodate_sim.qrpt VerilogHDL_alarmclock\date\datecontrol\cmp_state.ini VerilogHDL_alarmclock\date\datecontrol\datecontrol.asm.rpt VerilogHDL_alarmclock\date\datecontrol\datecontrol.bsf VerilogHDL_alarmclock\date\datecontrol\datecontrol.done VerilogHDL_alarmclock\date\datecontrol\datecontrol.fit.eqn VerilogHDL_alarmclock\date\datecontrol\datecontrol.fit.rpt VerilogHDL_alarmclock\date\datecontrol\datecontrol.fit.summary VerilogHDL_alarmclock\date\datecontrol\datecontrol.flow.rpt VerilogHDL_alarmclock\date\datecontrol\datecontrol.map.eqn VerilogHDL_alarmclock\date\datecontrol\datecontrol.map.rpt VerilogHDL_alarmclock\date\datecontrol\datecontrol.map.summary VerilogHDL_alarmclock\date\datecontrol\datecontrol.pin VerilogHDL_alarmclock\date\datecontrol\datecontrol.pof VerilogHDL_alarmclock\date\datecontrol\datecontrol.qpf VerilogHDL_alarmclock\date\datecontrol\datecontrol.qsf VerilogHDL_alarmclock\date\datecontrol\datecontrol.qws VerilogHDL_alarmclock\date\datecontrol\datecontrol.sim.rpt VerilogHDL_alarmclock\date\datecontrol\datecontrol.tan.rpt VerilogHDL_alarmclock\date\datecontrol\datecontrol.tan.summary VerilogHDL_alarmclock\date\datecontrol\datecontrol.v VerilogHDL_alarmclock\date\datecontrol\datecontrol.vwf VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.(0).cnf.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.(0).cnf.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.asm.qmsg VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.cmp.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.cmp.ddb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.cmp.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.cmp.rdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.cmp.tdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.cmp0.ddb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.db_info VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.eco.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.eds_overflow VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.fit.qmsg VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.hier_info VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.hif VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.map.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.map.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.map.qmsg VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.pre_map.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.pre_map.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.psp VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.rtlv.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.rtlv_sg.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.rtlv_sg_swap.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sgdiff.cdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sgdiff.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sim.hdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sim.qmsg VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sim.rdb VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sim.vwf VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sld_design_entry.sci VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.sld_design_entry_dsc.sci VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.syn_hier_info VerilogHDL_alarmclock\date\datecontrol\db\datecontrol.tan.qmsg VerilogHDL_alarmclock\date\datecontrol\db\datecontrol_cmp.qrpt VerilogHDL_alarmclock\date\datecontrol\db\datecontrol_sim.qrpt VerilogHDL_alarmclock\date\date_main\autodate.v VerilogHDL_alarmclock\date\date_main\cmp_state.ini VerilogHDL_alarmclock\date\date_main\datecontrol.v VerilogHDL_alarmclock\date\date_main\date_main.asm.rpt VerilogHDL_alarmclock\date\date_main\date_main.bdf VerilogHDL_alarmclock\date\date_main\date_main.bsf VerilogHDL_alarmclock\date\date_main\date_main.done VerilogHDL_alarmclock\date\date_main\date_main.fit.eqn VerilogHDL_alarmclock\date\date_main\date_main.fit.rpt VerilogHDL_alarmclock\date\date_main\date_main.fit.summary VerilogHDL_alarmclock\date\date_main\date_main.flow.rpt VerilogHDL_alarmclock\date\date_main\date_main.map.eqn VerilogHDL_alarmclock\date\date_main\date_main.map.rpt VerilogHDL_alarmclock\date\date_main\date_main.map.summary VerilogHDL_alarmclock\date\date_main\date_main.pin VerilogHDL_alarmclock\date\date_main\date_main.pof VerilogHDL_alarmclock\date\date_main\date_main.qpf VerilogHDL_alarmclock\date\date_main\date_main.qsf VerilogHDL_alarmclock\date\date_main\date_main.qws VerilogHDL_alarmclock\date\date_main\date_main.sim.rpt VerilogHDL_alarmclock\date\date_main\date_main.tan.rpt VerilogHDL_alarmclock\date\date_main\date_main.tan.summary VerilogHDL_alarmclock\date\date_main\date_main.v VerilogHDL_alarmclock\date\date_main\date_main.vwf VerilogHDL_alarmclock\date\date_main\db\date_main.(0).cnf.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.(0).cnf.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.(1).cnf.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.(1).cnf.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.(2).cnf.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.(2).cnf.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.(3).cnf.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.(3).cnf.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.(4).cnf.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.(4).cnf.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.asm.qmsg VerilogHDL_alarmclock\date\date_main\db\date_main.cmp.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.cmp.ddb VerilogHDL_alarmclock\date\date_main\db\date_main.cmp.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.cmp.rdb VerilogHDL_alarmclock\date\date_main\db\date_main.cmp.tdb VerilogHDL_alarmclock\date\date_main\db\date_main.cmp0.ddb VerilogHDL_alarmclock\date\date_main\db\date_main.db_info VerilogHDL_alarmclock\date\date_main\db\date_main.eco.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.eds_overflow VerilogHDL_alarmclock\date\date_main\db\date_main.fit.qmsg VerilogHDL_alarmclock\date\date_main\db\date_main.hier_info VerilogHDL_alarmclock\date\date_main\db\date_main.hif VerilogHDL_alarmclock\date\date_main\db\date_main.map.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.map.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.map.qmsg VerilogHDL_alarmclock\date\date_main\db\date_main.pre_map.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.pre_map.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.psp VerilogHDL_alarmclock\date\date_main\db\date_main.rtlv.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.rtlv_sg.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.rtlv_sg_swap.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.sgdiff.cdb VerilogHDL_alarmclock\date\date_main\db\date_main.sgdiff.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.sim.hdb VerilogHDL_alarmclock\date\date_main\db\date_main.sim.qmsg VerilogHDL_alarmclock\date\date_main\db\date_main.sim.rdb VerilogHDL_alarmclock\date\date_main\db\date_main.sim.vwf VerilogHDL_alarmclock\date\date_main\db\date_main.sld_design_entry.sci VerilogHDL_alarmclock\date\date_main\db\date_main.sld_design_entry_dsc.sci VerilogHDL_alarmclock\date\date_main\db\date_main.syn_hier_info VerilogHDL_alarmclock\date\date_main\db\date_main.tan.qmsg VerilogHDL_alarmclock\date\date_main\db\date_main_cmp.qrpt VerilogHDL_alarmclock\date\date_main\db\date_main_sim.qrpt VerilogHDL_alarmclock\date\date_main\setdate.v VerilogHDL_alarmclock\date\setdate\cmp_state.ini VerilogHDL_alarmclock\date\setdate\db\setdate.(0).cnf.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.(0).cnf.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.(1).cnf.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.(1).cnf.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.asm.qmsg VerilogHDL_alarmclock\date\setdate\db\setdate.cmp.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.cmp.ddb VerilogHDL_alarmclock\date\setdate\db\setdate.cmp.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.cmp.rdb VerilogHDL_alarmclock\date\setdate\db\setdate.cmp.tdb VerilogHDL_alarmclock\date\setdate\db\setdate.cmp0.ddb VerilogHDL_alarmclock\date\setdate\db\setdate.db_info VerilogHDL_alarmclock\date\setdate\db\setdate.eco.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.eds_overflow VerilogHDL_alarmclock\date\setdate\db\setdate.fit.qmsg VerilogHDL_alarmclock\date\setdate\db\setdate.hier_info VerilogHDL_alarmclock\date\setdate\db\setdate.hif VerilogHDL_alarmclock\date\setdate\db\setdate.map.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.map.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.map.qmsg VerilogHDL_alarmclock\date\setdate\db\setdate.pre_map.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.pre_map.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.psp VerilogHDL_alarmclock\date\setdate\db\setdate.rtlv.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.rtlv_sg.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.rtlv_sg_swap.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.sgdiff.cdb VerilogHDL_alarmclock\date\setdate\db\setdate.sgdiff.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.sim.hdb VerilogHDL_alarmclock\date\setdate\db\setdate.sim.qmsg VerilogHDL_alarmclock\date\setdate\db\setdate.sim.rdb VerilogHDL_alarmclock\date\setdate\db\setdate.sim.vwf VerilogHDL_alarmclock\date\setdate\db\setdate.sld_design_entry.sci VerilogHDL_alarmclock\date\setdate\db\setdate.sld_design_entry_dsc.sci VerilogHDL_alarmclock\date\setdate\db\setdate.syn_hier_info VerilogHDL_alarmclock\date\setdate\db\setdate.tan.qmsg VerilogHDL_alarmclock\date\setdate\db\setdate_cmp.qrpt VerilogHDL_alarmclock\date\setdate\db\setdate_sim.qrpt VerilogHDL_alarmclock\date\setdate\setdate.asm.rpt VerilogHDL_alarmclock\date\setdate\setdate.bsf VerilogHDL_alarmclock\date\setdate\setdate.done VerilogHDL_alarmclock\date\setdate\setdate.fit.eqn VerilogHDL_alarmclock\date\setdate\setdate.fit.rpt VerilogHDL_alarmclock\date\setdate\setdate.fit.summary VerilogHDL_alarmclock\date\setdate\setdate.flow.rpt VerilogHDL_alarmclock\date\setdate\setdate.map.eqn VerilogHDL_alarmclock\date\setdate\setdate.map.rpt VerilogHDL_alarmclock\date\setdate\setdate.map.summary VerilogHDL_alarmclock\date\setdate\setdate.pin VerilogHDL_alarmclock\date\setdate\setdate.pof VerilogHDL_alarmclock\date\setdate\setdate.qpf VerilogHDL_alarmclock\date\setdate\setdate.qsf VerilogHDL_alarmclock\date\setdate\setdate.qws VerilogHDL_alarmclock\date\setdate\setdate.sim.rpt VerilogHDL_alarmclock\date\setdate\setdate.tan.rpt VerilogHDL_alarmclock\date\setdate\setdate.tan.summary VerilogHDL_alarmclock\date\setdate\setdate.v VerilogHDL_alarmclock\date\setdate\setdate.vwf VerilogHDL_alarmclock\disp_data_mux\cmp_state.ini VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.(0).cnf.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.(0).cnf.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.asm.qmsg VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.cmp.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.cmp.ddb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.cmp.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.cmp.rdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.cmp.tdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.cmp0.ddb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.db_info VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.eco.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.eds_overflow VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.fit.qmsg VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.hier_info VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.hif VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.map.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.map.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.map.qmsg VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.pre_map.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.pre_map.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.psp VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.rtlv.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.rtlv_sg.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.rtlv_sg_swap.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sgdiff.cdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sgdiff.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sim.hdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sim.qmsg VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sim.rdb VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sim.vwf VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sld_design_entry.sci VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.sld_design_entry_dsc.sci VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.syn_hier_info VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux.tan.qmsg VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux_cmp.qrpt VerilogHDL_alarmclock\disp_data_mux\db\disp_data_mux_sim.qrpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.asm.rpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.bsf VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.done VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.fit.eqn VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.fit.rpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.fit.summary VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.flow.rpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.map.eqn VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.map.rpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.map.summary VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.pin VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.pof VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.qpf VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.qsf VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.qws VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.sim.rpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.tan.rpt VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.tan.summary VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.v VerilogHDL_alarmclock\disp_data_mux\disp_data_mux.vwf VerilogHDL_alarmclock\disp_select\cmp_state.ini VerilogHDL_alarmclock\disp_select\db\disp_select.db_info VerilogHDL_alarmclock\disp_select\db\disp_select.eco.cdb VerilogHDL_alarmclock\disp_select\db\disp_select.sld_design_entry.sci VerilogHDL_alarmclock\disp_select\disp_select.qpf VerilogHDL_alarmclock\disp_select\disp_select.qsf VerilogHDL_alarmclock\disp_select\disp_select.qws VerilogHDL_alarmclock\disp_select\disp_select.v VerilogHDL_alarmclock\fdiv\cmp_state.ini VerilogHDL_alarmclock\fdiv\db\fdiv.(0).cnf.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.(0).cnf.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.(1).cnf.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.(1).cnf.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.(2).cnf.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.(2).cnf.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.(3).cnf.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.(3).cnf.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.(4).cnf.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.(4).cnf.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.asm.qmsg VerilogHDL_alarmclock\fdiv\db\fdiv.cmp.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.cmp.ddb VerilogHDL_alarmclock\fdiv\db\fdiv.cmp.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.cmp.rdb VerilogHDL_alarmclock\fdiv\db\fdiv.cmp.tdb VerilogHDL_alarmclock\fdiv\db\fdiv.cmp0.ddb VerilogHDL_alarmclock\fdiv\db\fdiv.db_info VerilogHDL_alarmclock\fdiv\db\fdiv.eco.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.eds_overflow VerilogHDL_alarmclock\fdiv\db\fdiv.fit.qmsg VerilogHDL_alarmclock\fdiv\db\fdiv.hier_info VerilogHDL_alarmclock\fdiv\db\fdiv.hif VerilogHDL_alarmclock\fdiv\db\fdiv.map.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.map.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.map.qmsg VerilogHDL_alarmclock\fdiv\db\fdiv.pre_map.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.pre_map.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.psp VerilogHDL_alarmclock\fdiv\db\fdiv.rtlv.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.rtlv_sg.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.rtlv_sg_swap.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.sgdiff.cdb VerilogHDL_alarmclock\fdiv\db\fdiv.sgdiff.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.sim.hdb VerilogHDL_alarmclock\fdiv\db\fdiv.sim.qmsg VerilogHDL_alarmclock\fdiv\db\fdiv.sim.rdb VerilogHDL_alarmclock\fdiv\db\fdiv.sim.vwf VerilogHDL_alarmclock\fdiv\db\fdiv.sld_design_entry.sci VerilogHDL_alarmclock\fdiv\db\fdiv.sld_design_entry_dsc.sci VerilogHDL_alarmclock\fdiv\db\fdiv.syn_hier_info VerilogHDL_alarmclock\fdiv\db\fdiv.tan.qmsg VerilogHDL_alarmclock\fdiv\db\fdiv_cmp.qrpt VerilogHDL_alarmclock\fdiv\db\fdiv_sim.qrpt VerilogHDL_alarmclock\fdiv\fdiv.asm.rpt VerilogHDL_alarmclock\fdiv\fdiv.bsf VerilogHDL_alarmclock\fdiv\fdiv.done VerilogHDL_alarmclock\fdiv\fdiv.fit.eqn VerilogHDL_alarmclock\fdiv\fdiv.fit.rpt VerilogHDL_alarmclock\fdiv\fdiv.fit.summary VerilogHDL_alarmclock\fdiv\fdiv.flow.rpt VerilogHDL_alarmclock\fdiv\fdiv.map.eqn VerilogHDL_alarmclock\fdiv\fdiv.map.rpt VerilogHDL_alarmclock\fdiv\fdiv.map.summary VerilogHDL_alarmclock\fdiv\fdiv.pin VerilogHDL_alarmclock\fdiv\fdiv.pof VerilogHDL_alarmclock\fdiv\fdiv.qpf VerilogHDL_alarmclock\fdiv\fdiv.qsf VerilogHDL_alarmclock\fdiv\fdiv.qws VerilogHDL_alarmclock\fdiv\fdiv.sim.rpt VerilogHDL_alarmclock\fdiv\fdiv.tan.rpt VerilogHDL_alarmclock\fdiv\fdiv.tan.summary VerilogHDL_alarmclock\fdiv\fdiv.v VerilogHDL_alarmclock\fdiv\fdiv.vwf VerilogHDL_alarmclock\main\alarmclock.v VerilogHDL_alarmclock\main\autodate.v VerilogHDL_alarmclock\main\cmp_state.ini VerilogHDL_alarmclock\main\datecontrol.v VerilogHDL_alarmclock\main\date_main.v VerilogHDL_alarmclock\main\db\cntr_e08.tdf VerilogHDL_alarmclock\main\db\cntr_jd7.tdf VerilogHDL_alarmclock\main\db\main.(0).cnf.cdb VerilogHDL_alarmclock\main\db\main.(0).cnf.hdb VerilogHDL_alarmclock\main\db\main.(1).cnf.cdb VerilogHDL_alarmclock\main\db\main.(1).cnf.hdb VerilogHDL_alarmclock\main\db\main.(10).cnf.cdb VerilogHDL_alarmclock\main\db\main.(10).cnf.hdb VerilogHDL_alarmclock\main\db\main.(11).cnf.cdb VerilogHDL_alarmclock\main\db\main.(11).cnf.hdb VerilogHDL_alarmclock\main\db\main.(12).cnf.cdb VerilogHDL_alarmclock\main\db\main.(12).cnf.hdb VerilogHDL_alarmclock\main\db\main.(13).cnf.cdb VerilogHDL_alarmclock\main\db\main.(13).cnf.hdb VerilogHDL_alarmclock\main\db\main.(14).cnf.cdb VerilogHDL_alarmclock\main\db\main.(14).cnf.hdb VerilogHDL_alarmclock\main\db\main.(15).cnf.cdb VerilogHDL_alarmclock\main\db\main.(15).cnf.hdb VerilogHDL_alarmclock\main\db\main.(16).cnf.cdb VerilogHDL_alarmclock\main\db\main.(16).cnf.hdb VerilogHDL_alarmclock\main\db\main.(17).cnf.cdb VerilogHDL_alarmclock\main\db\main.(17).cnf.hdb VerilogHDL_alarmclock\main\db\main.(18).cnf.cdb VerilogHDL_alarmclock\main\db\main.(18).cnf.hdb VerilogHDL_alarmclock\main\db\main.(19).cnf.cdb VerilogHDL_alarmclock\main\db\main.(19).cnf.hdb VerilogHDL_alarmclock\main\db\main.(2).cnf.cdb VerilogHDL_alarmclock\main\db\main.(2).cnf.hdb VerilogHDL_alarmclock\main\db\main.(20).cnf.cdb VerilogHDL_alarmclock\main\db\main.(20).cnf.hdb VerilogHDL_alarmclock\main\db\main.(21).cnf.cdb VerilogHDL_alarmclock\main\db\main.(21).cnf.hdb VerilogHDL_alarmclock\main\db\main.(22).cnf.cdb VerilogHDL_alarmclock\main\db\main.(22).cnf.hdb VerilogHDL_alarmclock\main\db\main.(23).cnf.cdb VerilogHDL_alarmclock\main\db\main.(23).cnf.hdb VerilogHDL_alarmclock\main\db\main.(3).cnf.cdb VerilogHDL_alarmclock\main\db\main.(3).cnf.hdb VerilogHDL_alarmclock\main\db\main.(4).cnf.cdb VerilogHDL_alarmclock\main\db\main.(4).cnf.hdb VerilogHDL_alarmclock\main\db\main.(5).cnf.cdb VerilogHDL_alarmclock\main\db\main.(5).cnf.hdb VerilogHDL_alarmclock\main\db\main.(6).cnf.cdb VerilogHDL_alarmclock\main\db\main.(6).cnf.hdb VerilogHDL_alarmclock\main\db\main.(7).cnf.cdb VerilogHDL_alarmclock\main\db\main.(7).cnf.hdb VerilogHDL_alarmclock\main\db\main.(8).cnf.cdb VerilogHDL_alarmclock\main\db\main.(8).cnf.hdb VerilogHDL_alarmclock\main\db\main.(9).cnf.cdb VerilogHDL_alarmclock\main\db\main.(9).cnf.hdb VerilogHDL_alarmclock\main\db\main.asm.qmsg VerilogHDL_alarmclock\main\db\main.cmp.cdb VerilogHDL_alarmclock\main\db\main.cmp.ddb VerilogHDL_alarmclock\main\db\main.cmp.hdb VerilogHDL_alarmclock\main\db\main.cmp.rdb VerilogHDL_alarmclock\main\db\main.cmp.tdb VerilogHDL_alarmclock\main\db\main.cmp0.ddb VerilogHDL_alarmclock\main\db\main.db_info VerilogHDL_alarmclock\main\db\main.eco.cdb VerilogHDL_alarmclock\main\db\main.eds_overflow VerilogHDL_alarmclock\main\db\main.fit.qmsg VerilogHDL_alarmclock\main\db\main.hier_info VerilogHDL_alarmclock\main\db\main.hif VerilogHDL_alarmclock\main\db\main.icc VerilogHDL_alarmclock\main\db\main.map.cdb VerilogHDL_alarmclock\main\db\main.map.hdb VerilogHDL_alarmclock\main\db\main.map.qmsg VerilogHDL_alarmclock\main\db\main.pre_map.cdb VerilogHDL_alarmclock\main\db\main.pre_map.hdb VerilogHDL_alarmclock\main\db\main.psp VerilogHDL_alarmclock\main\db\main.rtlv.hdb VerilogHDL_alarmclock\main\db\main.rtlv_sg.cdb VerilogHDL_alarmclock\main\db\main.rtlv_sg_swap.cdb VerilogHDL_alarmclock\main\db\main.sgdiff.cdb VerilogHDL_alarmclock\main\db\main.sgdiff.hdb VerilogHDL_alarmclock\main\db\main.signalprobe.cdb VerilogHDL_alarmclock\main\db\main.sim.hdb VerilogHDL_alarmclock\main\db\main.sim.qmsg VerilogHDL_alarmclock\main\db\main.sim.rdb VerilogHDL_alarmclock\main\db\main.sim.vwf VerilogHDL_alarmclock\main\db\main.sld_design_entry.sci VerilogHDL_alarmclock\main\db\main.sld_design_entry_dsc.sci VerilogHDL_alarmclock\main\db\main.syn_hier_info VerilogHDL_alarmclock\main\db\main.tan.qmsg VerilogHDL_alarmclock\main\db\main_cmp.qrpt VerilogHDL_alarmclock\main\db\main_sim.qrpt VerilogHDL_alarmclock\main\disp_data_mux.v VerilogHDL_alarmclock\main\fdiv.v VerilogHDL_alarmclock\main\hour_counter.v VerilogHDL_alarmclock\main\main.asm.rpt VerilogHDL_alarmclock\main\main.bdf VerilogHDL_alarmclock\main\main.done VerilogHDL_alarmclock\main\main.fit.eqn VerilogHDL_alarmclock\main\main.fit.rpt VerilogHDL_alarmclock\main\main.fit.summary VerilogHDL_alarmclock\main\main.flow.rpt VerilogHDL_alarmclock\main\main.map.eqn VerilogHDL_alarmclock\main\main.map.rpt VerilogHDL_alarmclock\main\main.map.summary VerilogHDL_alarmclock\main\main.pin VerilogHDL_alarmclock\main\main.pof VerilogHDL_alarmclock\main\main.qpf VerilogHDL_alarmclock\main\main.qsf VerilogHDL_alarmclock\main\main.qws VerilogHDL_alarmclock\main\main.sim.rpt VerilogHDL_alarmclock\main\main.sof VerilogHDL_alarmclock\main\main.tan.rpt VerilogHDL_alarmclock\main\main.tan.summary VerilogHDL_alarmclock\main\main.v VerilogHDL_alarmclock\main\main.vwf VerilogHDL_alarmclock\main\maincontrol.v VerilogHDL_alarmclock\main\minute_counter.v VerilogHDL_alarmclock\main\second_counter.v VerilogHDL_alarmclock\main\setdate.v VerilogHDL_alarmclock\main\stopwatch.v VerilogHDL_alarmclock\main\timepiece_main.v VerilogHDL_alarmclock\main\timeset.v VerilogHDL_alarmclock\main\time_auto_and_set.v VerilogHDL_alarmclock\main\time_disp_select.v VerilogHDL_alarmclock\main\time_mux.v VerilogHDL_alarmclock\maincontrol\cmp_state.ini VerilogHDL_alarmclock\maincontrol\db\maincontrol.(0).cnf.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.(0).cnf.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.asm.qmsg VerilogHDL_alarmclock\maincontrol\db\maincontrol.cmp.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.cmp.ddb VerilogHDL_alarmclock\maincontrol\db\maincontrol.cmp.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.cmp.rdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.cmp.tdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.cmp0.ddb VerilogHDL_alarmclock\maincontrol\db\maincontrol.db_info VerilogHDL_alarmclock\maincontrol\db\maincontrol.eco.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.eds_overflow VerilogHDL_alarmclock\maincontrol\db\maincontrol.fit.qmsg VerilogHDL_alarmclock\maincontrol\db\maincontrol.hier_info VerilogHDL_alarmclock\maincontrol\db\maincontrol.hif VerilogHDL_alarmclock\maincontrol\db\maincontrol.map.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.map.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.map.qmsg VerilogHDL_alarmclock\maincontrol\db\maincontrol.pre_map.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.pre_map.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.psp VerilogHDL_alarmclock\maincontrol\db\maincontrol.rtlv.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.rtlv_sg.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.rtlv_sg_swap.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.sgdiff.cdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.sgdiff.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.sim.hdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.sim.qmsg VerilogHDL_alarmclock\maincontrol\db\maincontrol.sim.rdb VerilogHDL_alarmclock\maincontrol\db\maincontrol.sim.vwf VerilogHDL_alarmclock\maincontrol\db\maincontrol.sld_design_entry.sci VerilogHDL_alarmclock\maincontrol\db\maincontrol.sld_design_entry_dsc.sci VerilogHDL_alarmclock\maincontrol\db\maincontrol.syn_hier_info VerilogHDL_alarmclock\maincontrol\db\maincontrol.tan.qmsg VerilogHDL_alarmclock\maincontrol\db\maincontrol_cmp.qrpt VerilogHDL_alarmclock\maincontrol\db\maincontrol_sim.qrpt VerilogHDL_alarmclock\maincontrol\maincontrol.asm.rpt VerilogHDL_alarmclock\maincontrol\maincontrol.bsf VerilogHDL_alarmclock\maincontrol\maincontrol.done VerilogHDL_alarmclock\maincontrol\maincontrol.fit.eqn VerilogHDL_alarmclock\maincontrol\maincontrol.fit.rpt VerilogHDL_alarmclock\maincontrol\maincontrol.fit.summary VerilogHDL_alarmclock\maincontrol\maincontrol.flow.rpt VerilogHDL_alarmclock\maincontrol\maincontrol.map.eqn VerilogHDL_alarmclock\maincontrol\maincontrol.map.rpt VerilogHDL_alarmclock\maincontrol\maincontrol.map.summary VerilogHDL_alarmclock\maincontrol\maincontrol.pin VerilogHDL_alarmclock\maincontrol\maincontrol.pof VerilogHDL_alarmclock\maincontrol\maincontrol.qpf VerilogHDL_alarmclock\maincontrol\maincontrol.qsf VerilogHDL_alarmclock\maincontrol\maincontrol.qws VerilogHDL_alarmclock\maincontrol\maincontrol.sim.rpt VerilogHDL_alarmclock\maincontrol\maincontrol.tan.rpt VerilogHDL_alarmclock\maincontrol\maincontrol.tan.summary VerilogHDL_alarmclock\maincontrol\maincontrol.v VerilogHDL_alarmclock\maincontrol\maincontrol.vwf VerilogHDL_alarmclock\stopwatch\cmp_state.ini VerilogHDL_alarmclock\stopwatch\db\add_sub_8ph.tdf VerilogHDL_alarmclock\stopwatch\db\stopwatch.(0).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(0).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(1).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(1).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(2).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(2).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(3).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(3).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(4).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(4).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(5).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(5).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(6).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(6).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(7).cnf.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.(7).cnf.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.asm.qmsg VerilogHDL_alarmclock\stopwatch\db\stopwatch.cmp.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.cmp.ddb VerilogHDL_alarmclock\stopwatch\db\stopwatch.cmp.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.cmp.rdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.cmp.tdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.cmp0.ddb VerilogHDL_alarmclock\stopwatch\db\stopwatch.db_info VerilogHDL_alarmclock\stopwatch\db\stopwatch.eco.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.eds_overflow VerilogHDL_alarmclock\stopwatch\db\stopwatch.fit.qmsg VerilogHDL_alarmclock\stopwatch\db\stopwatch.hier_info VerilogHDL_alarmclock\stopwatch\db\stopwatch.hif VerilogHDL_alarmclock\stopwatch\db\stopwatch.map.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.map.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.map.qmsg VerilogHDL_alarmclock\stopwatch\db\stopwatch.pre_map.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.pre_map.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.psp VerilogHDL_alarmclock\stopwatch\db\stopwatch.rtlv.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.rtlv_sg.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.rtlv_sg_swap.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.sgdiff.cdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.sgdiff.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.sim.hdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.sim.qmsg VerilogHDL_alarmclock\stopwatch\db\stopwatch.sim.rdb VerilogHDL_alarmclock\stopwatch\db\stopwatch.sim.vwf VerilogHDL_alarmclock\stopwatch\db\stopwatch.sld_design_entry.sci VerilogHDL_alarmclock\stopwatch\db\stopwatch.sld_design_entry_dsc.sci VerilogHDL_alarmclock\stopwatch\db\stopwatch.syn_hier_info VerilogHDL_alarmclock\stopwatch\db\stopwatch.tan.qmsg VerilogHDL_alarmclock\stopwatch\db\stopwatch_cmp.qrpt VerilogHDL_alarmclock\stopwatch\db\stopwatch_sim.qrpt VerilogHDL_alarmclock\stopwatch\stopwatch.asm.rpt VerilogHDL_alarmclock\stopwatch\stopwatch.bsf VerilogHDL_alarmclock\stopwatch\stopwatch.done VerilogHDL_alarmclock\stopwatch\stopwatch.fit.eqn VerilogHDL_alarmclock\stopwatch\stopwatch.fit.rpt VerilogHDL_alarmclock\stopwatch\stopwatch.fit.summary VerilogHDL_alarmclock\stopwatch\stopwatch.flow.rpt VerilogHDL_alarmclock\stopwatch\stopwatch.map.eqn VerilogHDL_alarmclock\stopwatch\stopwatch.map.rpt VerilogHDL_alarmclock\stopwatch\stopwatch.map.summary VerilogHDL_alarmclock\stopwatch\stopwatch.pin VerilogHDL_alarmclock\stopwatch\stopwatch.pof VerilogHDL_alarmclock\stopwatch\stopwatch.qpf VerilogHDL_alarmclock\stopwatch\stopwatch.qsf VerilogHDL_alarmclock\stopwatch\stopwatch.qws VerilogHDL_alarmclock\stopwatch\stopwatch.sim.rpt VerilogHDL_alarmclock\stopwatch\stopwatch.tan.rpt VerilogHDL_alarmclock\stopwatch\stopwatch.tan.summary VerilogHDL_alarmclock\stopwatch\stopwatch.v VerilogHDL_alarmclock\stopwatch\stopwatch.vwf VerilogHDL_alarmclock\timepiece\hour_counter\cmp_state.ini VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.(0).cnf.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.(0).cnf.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.(1).cnf.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.(1).cnf.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.asm.qmsg VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.cmp.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.cmp.ddb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.cmp.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.cmp.rdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.cmp.tdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.cmp0.ddb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.db_info VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.eco.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.eds_overflow VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.fit.qmsg VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.hier_info VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.hif VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.map.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.map.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.map.qmsg VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.pre_map.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.pre_map.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.psp VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.rtlv.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.rtlv_sg.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.rtlv_sg_swap.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sgdiff.cdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sgdiff.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sim.hdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sim.qmsg VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sim.rdb VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sim.vwf VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sld_design_entry.sci VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.sld_design_entry_dsc.sci VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.syn_hier_info VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter.tan.qmsg VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter_cmp.qrpt VerilogHDL_alarmclock\timepiece\hour_counter\db\hour_counter_sim.qrpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.asm.rpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.bsf VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.done VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.fit.eqn VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.fit.rpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.fit.summary VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.flow.rpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.map.eqn VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.map.rpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.map.summary VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.pin VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.pof VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.qpf VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.qsf VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.qws VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.sim.rpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.tan.rpt VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.tan.summary VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.v VerilogHDL_alarmclock\timepiece\hour_counter\hour_counter.vwf VerilogHDL_alarmclock\timepiece\minute_counter\cmp_state.ini VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.(0).cnf.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.(0).cnf.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.(1).cnf.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.(1).cnf.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.asm.qmsg VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.cmp.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.cmp.ddb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.cmp.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.cmp.rdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.cmp.tdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.cmp0.ddb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.db_info VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.eco.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.eds_overflow VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.fit.qmsg VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.hier_info VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.hif VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.map.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.map.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.map.qmsg VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.pre_map.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.pre_map.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.psp VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.rtlv.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.rtlv_sg.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.rtlv_sg_swap.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sgdiff.cdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sgdiff.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sim.hdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sim.qmsg VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sim.rdb VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sim.vwf VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sld_design_entry.sci VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.sld_design_entry_dsc.sci VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.syn_hier_info VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter.tan.qmsg VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter_cmp.qrpt VerilogHDL_alarmclock\timepiece\minute_counter\db\minute_counter_sim.qrpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.asm.rpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.bsf VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.done VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.fit.eqn VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.fit.rpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.fit.summary VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.flow.rpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.map.eqn VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.map.rpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.map.summary VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.pin VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.pof VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.qpf VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.qsf VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.qws VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.sim.rpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.tan.rpt VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.tan.summary VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.v VerilogHDL_alarmclock\timepiece\minute_counter\minute_counter.vwf VerilogHDL_alarmclock\timepiece\second_counter\cmp_state.ini VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.(0).cnf.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.(0).cnf.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.(1).cnf.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.(1).cnf.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.asm.qmsg VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.cmp.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.cmp.ddb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.cmp.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.cmp.rdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.cmp.tdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.cmp0.ddb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.db_info VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.eco.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.eds_overflow VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.fit.qmsg VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.hier_info VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.hif VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.map.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.map.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.map.qmsg VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.pre_map.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.pre_map.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.psp VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.rtlv.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.rtlv_sg.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.rtlv_sg_swap.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sgdiff.cdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sgdiff.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sim.hdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sim.qmsg VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sim.rdb VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sim.vwf VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sld_design_entry.sci VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.sld_design_entry_dsc.sci VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.syn_hier_info VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter.tan.qmsg VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter_cmp.qrpt VerilogHDL_alarmclock\timepiece\second_counter\db\second_counter_sim.qrpt VerilogHDL_alarmclock\timepiece\second_counter\main.bdf VerilogHDL_alarmclock\timepiece\second_counter\second_counter.asm.rpt VerilogHDL_alarmclock\timepiece\second_counter\second_counter.bsf VerilogHDL_alarmclock\timepiece\second_counter\second_counter.done VerilogHDL_alarmclock\timepiece\second_counter\second_counter.fit.eqn VerilogHDL_alarmclock\timepiece\second_counter\second_counter.fit.rpt VerilogHDL_alarmclock\timepiece\second_counter\second_counter.fit.summary VerilogHDL_alarmclock\timepiece\second_counter\second_counter.flow.rpt VerilogHDL_alarmclock\timepiece\second_counter\second_counter.map.eqn VerilogHDL_alarmclock\timepiece\second_counter\second_counter.map.rpt VerilogHDL_alarmclock\timepiece\second_counter\second_counter.map.summary VerilogHDL_alarmclock\timepiece\second_counter\second_counter.pin VerilogHDL_alarmclock\timepiece\second_counter\second_counter.pof VerilogHDL_alarmclock\timepiece\second_counter\second_counter.qpf VerilogHDL_alarmclock\timepiece\second_counter\second_counter.qsf VerilogHDL_alarmclock\timepiece\second_counter\second_counter.qws VerilogHDL_alarmclock\timepiece\second_counter\second_counter.sim.rpt VerilogHDL_alarmclock\timepiece\second_counter\second_counter.tan.rpt VerilogHDL_alarmclock\timepiece\second_counter\second_counter.tan.summary VerilogHDL_alarmclock\timepiece\second_counter\second_counter.v VerilogHDL_alarmclock\timepiece\second_counter\second_counter.vwf VerilogHDL_alarmclock\timepiece\timepiece_main\cmp_state.ini VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(0).cnf.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(0).cnf.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(1).cnf.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(1).cnf.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(2).cnf.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(2).cnf.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(3).cnf.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(3).cnf.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(4).cnf.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.(4).cnf.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.asm.qmsg VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.cmp.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.cmp.ddb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.cmp.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.cmp.rdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.cmp.tdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.cmp0.ddb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.db_info VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.eco.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.eds_overflow VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.fit.qmsg VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.hier_info VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.hif VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.map.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.map.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.map.qmsg VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.pre_map.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.pre_map.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.psp VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.rtlv.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.rtlv_sg.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.rtlv_sg_swap.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sgdiff.cdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sgdiff.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sim.hdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sim.qmsg VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sim.rdb VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sim.vwf VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sld_design_entry.sci VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.sld_design_entry_dsc.sci VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.syn_hier_info VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main.tan.qmsg VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main_cmp.qrpt VerilogHDL_alarmclock\timepiece\timepiece_main\db\timepiece_main_sim.qrpt VerilogHDL_alarmclock\timepiece\timepiece_main\hour_counter.v VerilogHDL_alarmclock\timepiece\timepiece_main\minute_counter.v VerilogHDL_alarmclock\timepiece\timepiece_main\second_counter.v VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.asm.rpt VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.bsf VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.done VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.fit.eqn VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.fit.rpt VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.fit.summary VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.flow.rpt VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.map.eqn VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.map.rpt VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.map.summary VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.pin VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.pof VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.qpf VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.qsf VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.qws VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.sim.rpt VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.tan.rpt VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.tan.summary VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.v VerilogHDL_alarmclock\timepiece\timepiece_main\timepiece_main.vwf VerilogHDL_alarmclock\timeset\cmp_state.ini VerilogHDL_alarmclock\timeset\db\timeset.(0).cnf.cdb VerilogHDL_alarmclock\timeset\db\timeset.(0).cnf.hdb VerilogHDL_alarmclock\timeset\db\timeset.(1).cnf.cdb VerilogHDL_alarmclock\timeset\db\timeset.(1).cnf.hdb VerilogHDL_alarmclock\timeset\db\timeset.asm.qmsg VerilogHDL_alarmclock\timeset\db\timeset.cmp.cdb VerilogHDL_alarmclock\timeset\db\timeset.cmp.ddb VerilogHDL_alarmclock\timeset\db\timeset.cmp.hdb VerilogHDL_alarmclock\timeset\db\timeset.cmp.rdb VerilogHDL_alarmclock\timeset\db\timeset.cmp.tdb VerilogHDL_alarmclock\timeset\db\timeset.cmp0.ddb VerilogHDL_alarmclock\timeset\db\timeset.db_info VerilogHDL_alarmclock\timeset\db\timeset.eco.cdb VerilogHDL_alarmclock\timeset\db\timeset.eds_overflow VerilogHDL_alarmclock\timeset\db\timeset.fit.qmsg VerilogHDL_alarmclock\timeset\db\timeset.hier_info VerilogHDL_alarmclock\timeset\db\timeset.hif VerilogHDL_alarmclock\timeset\db\timeset.map.cdb VerilogHDL_alarmclock\timeset\db\timeset.map.hdb VerilogHDL_alarmclock\timeset\db\timeset.map.qmsg VerilogHDL_alarmclock\timeset\db\timeset.pre_map.cdb VerilogHDL_alarmclock\timeset\db\timeset.pre_map.hdb VerilogHDL_alarmclock\timeset\db\timeset.psp VerilogHDL_alarmclock\timeset\db\timeset.rtlv.hdb VerilogHDL_alarmclock\timeset\db\timeset.rtlv_sg.cdb VerilogHDL_alarmclock\timeset\db\timeset.rtlv_sg_swap.cdb VerilogHDL_alarmclock\timeset\db\timeset.sgdiff.cdb VerilogHDL_alarmclock\timeset\db\timeset.sgdiff.hdb VerilogHDL_alarmclock\timeset\db\timeset.sim.hdb VerilogHDL_alarmclock\timeset\db\timeset.sim.qmsg VerilogHDL_alarmclock\timeset\db\timeset.sim.rdb VerilogHDL_alarmclock\timeset\db\timeset.sim.vwf VerilogHDL_alarmclock\timeset\db\timeset.sld_design_entry.sci VerilogHDL_alarmclock\timeset\db\timeset.sld_design_entry_dsc.sci VerilogHDL_alarmclock\timeset\db\timeset.syn_hier_info VerilogHDL_alarmclock\timeset\db\timeset.tan.qmsg VerilogHDL_alarmclock\timeset\db\timeset_cmp.qrpt VerilogHDL_alarmclock\timeset\db\timeset_sim.qrpt VerilogHDL_alarmclock\timeset\timeset.asm.rpt VerilogHDL_alarmclock\timeset\timeset.bsf VerilogHDL_alarmclock\timeset\timeset.done VerilogHDL_alarmclock\timeset\timeset.fit.eqn VerilogHDL_alarmclock\timeset\timeset.fit.rpt VerilogHDL_alarmclock\timeset\timeset.fit.summary VerilogHDL_alarmclock\timeset\timeset.flow.rpt VerilogHDL_alarmclock\timeset\timeset.map.eqn VerilogHDL_alarmclock\timeset\timeset.map.rpt VerilogHDL_alarmclock\timeset\timeset.map.summary VerilogHDL_alarmclock\timeset\timeset.pin VerilogHDL_alarmclock\timeset\timeset.pof VerilogHDL_alarmclock\timeset\timeset.qpf VerilogHDL_alarmclock\timeset\timeset.qsf VerilogHDL_alarmclock\timeset\timeset.qws VerilogHDL_alarmclock\timeset\timeset.sim.rpt VerilogHDL_alarmclock\timeset\timeset.tan.rpt VerilogHDL_alarmclock\timeset\timeset.tan.summary VerilogHDL_alarmclock\timeset\timeset.v VerilogHDL_alarmclock\timeset\timeset.vwf VerilogHDL_alarmclock\time_auto_and_set\cmp_state.ini VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(0).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(0).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(1).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(1).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(2).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(2).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(3).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(3).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(4).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(4).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(5).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(5).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(6).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(6).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(7).cnf.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.(7).cnf.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.asm.qmsg VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.cmp.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.cmp.ddb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.cmp.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.cmp.rdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.cmp.tdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.cmp0.ddb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.db_info VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.eco.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.eds_overflow VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.fit.qmsg VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.hier_info VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.hif VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.map.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.map.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.map.qmsg VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.pre_map.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.pre_map.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.psp VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.rtlv.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.rtlv_sg.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.rtlv_sg_swap.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sgdiff.cdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sgdiff.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sim.hdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sim.qmsg VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sim.rdb VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sim.vwf VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sld_design_entry.sci VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.sld_design_entry_dsc.sci VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.syn_hier_info VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set.tan.qmsg VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set_cmp.qrpt VerilogHDL_alarmclock\time_auto_and_set\db\time_auto_and_set_sim.qrpt VerilogHDL_alarmclock\time_auto_and_set\hour_counter.v VerilogHDL_alarmclock\time_auto_and_set\minute_counter.v VerilogHDL_alarmclock\time_auto_and_set\second_counter.v VerilogHDL_alarmclock\time_auto_and_set\time.v VerilogHDL_alarmclock\time_auto_and_set\timepiece_main.v VerilogHDL_alarmclock\time_auto_and_set\timeset.v VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.asm.rpt VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.bsf VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.done VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.fit.eqn VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.fit.rpt VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.fit.summary VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.flow.rpt VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.map.eqn VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.map.rpt VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.map.summary VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.pin VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.pof VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.qpf VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.qsf VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.qws VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.sim.rpt VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.tan.rpt VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.tan.summary VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.v VerilogHDL_alarmclock\time_auto_and_set\time_auto_and_set.vwf VerilogHDL_alarmclock\time_auto_and_set\time_mux.v VerilogHDL_alarmclock\time_disp_select\cmp_state.ini VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.(0).cnf.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.(0).cnf.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.asm.qmsg VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.cmp.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.cmp.ddb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.cmp.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.cmp.rdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.cmp.tdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.cmp0.ddb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.db_info VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.eco.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.eds_overflow VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.fit.qmsg VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.hier_info VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.hif VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.map.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.map.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.map.qmsg VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.pre_map.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.pre_map.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.psp VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.rtlv.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.rtlv_sg.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.rtlv_sg_swap.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sgdiff.cdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sgdiff.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sim.hdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sim.qmsg VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sim.rdb VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sim.vwf VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sld_design_entry.sci VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.sld_design_entry_dsc.sci VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.syn_hier_info VerilogHDL_alarmclock\time_disp_select\db\time_disp_select.tan.qmsg VerilogHDL_alarmclock\time_disp_select\db\time_disp_select_cmp.qrpt VerilogHDL_alarmclock\time_disp_select\db\time_disp_select_sim.qrpt VerilogHDL_alarmclock\time_disp_select\time_disp_select.asm.rpt VerilogHDL_alarmclock\time_disp_select\time_disp_select.bsf VerilogHDL_alarmclock\time_disp_select\time_disp_select.done VerilogHDL_alarmclock\time_disp_select\time_disp_select.fit.eqn VerilogHDL_alarmclock\time_disp_select\time_disp_select.fit.rpt VerilogHDL_alarmclock\time_disp_select\time_disp_select.fit.summary VerilogHDL_alarmclock\time_disp_select\time_disp_select.flow.rpt VerilogHDL_alarmclock\time_disp_select\time_disp_select.map.eqn VerilogHDL_alarmclock\time_disp_select\ti