文件名称:VerilogHDL_counter
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采用Verilog HDL语言编写的数字频率计,被测波形分别为方波、三角波和正弦波;采用6个数码管显示结果,三档量程可调,工程价值很高,
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压缩包 : 105230303veriloghdl_counter.rar 列表 VerilogHDL_counter\counter\cmp_state.ini VerilogHDL_counter\counter\counter.asm.rpt VerilogHDL_counter\counter\counter.bsf VerilogHDL_counter\counter\counter.done VerilogHDL_counter\counter\counter.fit.eqn VerilogHDL_counter\counter\counter.fit.rpt VerilogHDL_counter\counter\counter.fit.summary VerilogHDL_counter\counter\counter.flow.rpt VerilogHDL_counter\counter\counter.map.eqn VerilogHDL_counter\counter\counter.map.rpt VerilogHDL_counter\counter\counter.map.summary VerilogHDL_counter\counter\counter.pin VerilogHDL_counter\counter\counter.pof VerilogHDL_counter\counter\counter.qpf VerilogHDL_counter\counter\counter.qsf VerilogHDL_counter\counter\counter.qws VerilogHDL_counter\counter\counter.sim.rpt VerilogHDL_counter\counter\counter.tan.rpt VerilogHDL_counter\counter\counter.tan.summary VerilogHDL_counter\counter\counter.v VerilogHDL_counter\counter\counter.vwf VerilogHDL_counter\counter\counter10.v VerilogHDL_counter\counter\db\counter.(0).cnf.cdb VerilogHDL_counter\counter\db\counter.(0).cnf.hdb VerilogHDL_counter\counter\db\counter.(1).cnf.cdb VerilogHDL_counter\counter\db\counter.(1).cnf.hdb VerilogHDL_counter\counter\db\counter.(2).cnf.cdb VerilogHDL_counter\counter\db\counter.(2).cnf.hdb VerilogHDL_counter\counter\db\counter.asm.qmsg VerilogHDL_counter\counter\db\counter.cmp.cdb VerilogHDL_counter\counter\db\counter.cmp.ddb VerilogHDL_counter\counter\db\counter.cmp.hdb VerilogHDL_counter\counter\db\counter.cmp.rdb VerilogHDL_counter\counter\db\counter.cmp.tdb VerilogHDL_counter\counter\db\counter.cmp0.ddb VerilogHDL_counter\counter\db\counter.db_info VerilogHDL_counter\counter\db\counter.eco.cdb VerilogHDL_counter\counter\db\counter.eds_overflow VerilogHDL_counter\counter\db\counter.fit.qmsg VerilogHDL_counter\counter\db\counter.hier_info VerilogHDL_counter\counter\db\counter.hif VerilogHDL_counter\counter\db\counter.map.cdb VerilogHDL_counter\counter\db\counter.map.hdb VerilogHDL_counter\counter\db\counter.map.qmsg VerilogHDL_counter\counter\db\counter.pre_map.cdb VerilogHDL_counter\counter\db\counter.pre_map.hdb VerilogHDL_counter\counter\db\counter.psp VerilogHDL_counter\counter\db\counter.rtlv.hdb VerilogHDL_counter\counter\db\counter.rtlv_sg.cdb VerilogHDL_counter\counter\db\counter.rtlv_sg_swap.cdb VerilogHDL_counter\counter\db\counter.sgdiff.cdb VerilogHDL_counter\counter\db\counter.sgdiff.hdb VerilogHDL_counter\counter\db\counter.sim.hdb VerilogHDL_counter\counter\db\counter.sim.qmsg VerilogHDL_counter\counter\db\counter.sim.rdb VerilogHDL_counter\counter\db\counter.sim.vwf VerilogHDL_counter\counter\db\counter.sld_design_entry.sci VerilogHDL_counter\counter\db\counter.sld_design_entry_dsc.sci VerilogHDL_counter\counter\db\counter.syn_hier_info VerilogHDL_counter\counter\db\counter.tan.qmsg VerilogHDL_counter\counter\db\counter_cmp.qrpt VerilogHDL_counter\counter\db\counter_sim.qrpt VerilogHDL_counter\counter\Waveform1.vwf VerilogHDL_counter\data_mux\cmp_state.ini VerilogHDL_counter\data_mux\data_mux.asm.rpt VerilogHDL_counter\data_mux\data_mux.bsf VerilogHDL_counter\data_mux\data_mux.done VerilogHDL_counter\data_mux\data_mux.fit.eqn VerilogHDL_counter\data_mux\data_mux.fit.rpt VerilogHDL_counter\data_mux\data_mux.fit.summary VerilogHDL_counter\data_mux\data_mux.flow.rpt VerilogHDL_counter\data_mux\data_mux.map.eqn VerilogHDL_counter\data_mux\data_mux.map.rpt VerilogHDL_counter\data_mux\data_mux.map.summary VerilogHDL_counter\data_mux\data_mux.pin VerilogHDL_counter\data_mux\data_mux.pof VerilogHDL_counter\data_mux\data_mux.qpf VerilogHDL_counter\data_mux\data_mux.qsf VerilogHDL_counter\data_mux\data_mux.qws VerilogHDL_counter\data_mux\data_mux.sim.rpt VerilogHDL_counter\data_mux\data_mux.tan.rpt VerilogHDL_counter\data_mux\data_mux.tan.summary VerilogHDL_counter\data_mux\data_mux.v VerilogHDL_counter\data_mux\data_mux.vwf VerilogHDL_counter\data_mux\db\data_mux.(0).cnf.cdb VerilogHDL_counter\data_mux\db\data_mux.(0).cnf.hdb VerilogHDL_counter\data_mux\db\data_mux.asm.qmsg VerilogHDL_counter\data_mux\db\data_mux.cmp.cdb VerilogHDL_counter\data_mux\db\data_mux.cmp.ddb VerilogHDL_counter\data_mux\db\data_mux.cmp.hdb VerilogHDL_counter\data_mux\db\data_mux.cmp.rdb VerilogHDL_counter\data_mux\db\data_mux.cmp.tdb VerilogHDL_counter\data_mux\db\data_mux.cmp0.ddb VerilogHDL_counter\data_mux\db\data_mux.db_info VerilogHDL_counter\data_mux\db\data_mux.eco.cdb VerilogHDL_counter\data_mux\db\data_mux.eds_overflow VerilogHDL_counter\data_mux\db\data_mux.fit.qmsg VerilogHDL_counter\data_mux\db\data_mux.hier_info VerilogHDL_counter\data_mux\db\data_mux.hif VerilogHDL_counter\data_mux\db\data_mux.map.cdb VerilogHDL_counter\data_mux\db\data_mux.map.hdb VerilogHDL_counter\data_mux\db\data_mux.map.qmsg VerilogHDL_counter\data_mux\db\data_mux.pre_map.cdb VerilogHDL_counter\data_mux\db\data_mux.pre_map.hdb VerilogHDL_counter\data_mux\db\data_mux.psp VerilogHDL_counter\data_mux\db\data_mux.rtlv.hdb VerilogHDL_counter\data_mux\db\data_mux.rtlv_sg.cdb VerilogHDL_counter\data_mux\db\data_mux.rtlv_sg_swap.cdb VerilogHDL_counter\data_mux\db\data_mux.sgdiff.cdb VerilogHDL_counter\data_mux\db\data_mux.sgdiff.hdb VerilogHDL_counter\data_mux\db\data_mux.sim.hdb VerilogHDL_counter\data_mux\db\data_mux.sim.qmsg VerilogHDL_counter\data_mux\db\data_mux.sim.rdb VerilogHDL_counter\data_mux\db\data_mux.sim.vwf VerilogHDL_counter\data_mux\db\data_mux.sld_design_entry.sci VerilogHDL_counter\data_mux\db\data_mux.sld_design_entry_dsc.sci VerilogHDL_counter\data_mux\db\data_mux.syn_hier_info VerilogHDL_counter\data_mux\db\data_mux.tan.qmsg VerilogHDL_counter\data_mux\db\data_mux_cmp.qrpt VerilogHDL_counter\data_mux\db\data_mux_sim.qrpt VerilogHDL_counter\dispdecoder\cmp_state.ini VerilogHDL_counter\dispdecoder\db\dispdecoder.(0).cnf.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.(0).cnf.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.asm.qmsg VerilogHDL_counter\dispdecoder\db\dispdecoder.cmp.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.cmp.ddb VerilogHDL_counter\dispdecoder\db\dispdecoder.cmp.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.cmp.rdb VerilogHDL_counter\dispdecoder\db\dispdecoder.cmp.tdb VerilogHDL_counter\dispdecoder\db\dispdecoder.cmp0.ddb VerilogHDL_counter\dispdecoder\db\dispdecoder.db_info VerilogHDL_counter\dispdecoder\db\dispdecoder.eco.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.eds_overflow VerilogHDL_counter\dispdecoder\db\dispdecoder.fit.qmsg VerilogHDL_counter\dispdecoder\db\dispdecoder.hier_info VerilogHDL_counter\dispdecoder\db\dispdecoder.hif VerilogHDL_counter\dispdecoder\db\dispdecoder.map.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.map.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.map.qmsg VerilogHDL_counter\dispdecoder\db\dispdecoder.pre_map.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.pre_map.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.psp VerilogHDL_counter\dispdecoder\db\dispdecoder.rtlv.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.rtlv_sg.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.rtlv_sg_swap.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.sgdiff.cdb VerilogHDL_counter\dispdecoder\db\dispdecoder.sgdiff.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.sim.hdb VerilogHDL_counter\dispdecoder\db\dispdecoder.sim.qmsg VerilogHDL_counter\dispdecoder\db\dispdecoder.sim.rdb VerilogHDL_counter\dispdecoder\db\dispdecoder.sim.vwf VerilogHDL_counter\dispdecoder\db\dispdecoder.sld_design_entry.sci VerilogHDL_counter\dispdecoder\db\dispdecoder.sld_design_entry_dsc.sci VerilogHDL_counter\dispdecoder\db\dispdecoder.syn_hier_info VerilogHDL_counter\dispdecoder\db\dispdecoder.tan.qmsg VerilogHDL_counter\dispdecoder\db\dispdecoder_cmp.qrpt VerilogHDL_counter\dispdecoder\db\dispdecoder_sim.qrpt VerilogHDL_counter\dispdecoder\dispdecoder.asm.rpt VerilogHDL_counter\dispdecoder\dispdecoder.bsf VerilogHDL_counter\dispdecoder\dispdecoder.done VerilogHDL_counter\dispdecoder\dispdecoder.fit.eqn VerilogHDL_counter\dispdecoder\dispdecoder.fit.rpt VerilogHDL_counter\dispdecoder\dispdecoder.fit.summary VerilogHDL_counter\dispdecoder\dispdecoder.flow.rpt VerilogHDL_counter\dispdecoder\dispdecoder.map.eqn VerilogHDL_counter\dispdecoder\dispdecoder.map.rpt VerilogHDL_counter\dispdecoder\dispdecoder.map.summary VerilogHDL_counter\dispdecoder\dispdecoder.pin VerilogHDL_counter\dispdecoder\dispdecoder.pof VerilogHDL_counter\dispdecoder\dispdecoder.qpf VerilogHDL_counter\dispdecoder\dispdecoder.qsf VerilogHDL_counter\dispdecoder\dispdecoder.qws VerilogHDL_counter\dispdecoder\dispdecoder.sim.rpt VerilogHDL_counter\dispdecoder\dispdecoder.tan.rpt VerilogHDL_counter\dispdecoder\dispdecoder.tan.summary VerilogHDL_counter\dispdecoder\dispdecoder.v VerilogHDL_counter\dispdecoder\dispdecoder.vwf VerilogHDL_counter\dispselect\cmp_state.ini VerilogHDL_counter\dispselect\db\dispselect.(0).cnf.cdb VerilogHDL_counter\dispselect\db\dispselect.(0).cnf.hdb VerilogHDL_counter\dispselect\db\dispselect.asm.qmsg VerilogHDL_counter\dispselect\db\dispselect.cmp.cdb VerilogHDL_counter\dispselect\db\dispselect.cmp.ddb VerilogHDL_counter\dispselect\db\dispselect.cmp.hdb VerilogHDL_counter\dispselect\db\dispselect.cmp.rdb VerilogHDL_counter\dispselect\db\dispselect.cmp.tdb VerilogHDL_counter\dispselect\db\dispselect.cmp0.ddb VerilogHDL_counter\dispselect\db\dispselect.db_info VerilogHDL_counter\dispselect\db\dispselect.eco.cdb VerilogHDL_counter\dispselect\db\dispselect.eds_overflow VerilogHDL_counter\dispselect\db\dispselect.fit.qmsg VerilogHDL_counter\dispselect\db\dispselect.hier_info VerilogHDL_counter\dispselect\db\dispselect.hif VerilogHDL_counter\dispselect\db\dispselect.map.cdb VerilogHDL_counter\dispselect\db\dispselect.map.hdb VerilogHDL_counter\dispselect\db\dispselect.map.qmsg VerilogHDL_counter\dispselect\db\dispselect.pre_map.cdb VerilogHDL_counter\dispselect\db\dispselect.pre_map.hdb VerilogHDL_counter\dispselect\db\dispselect.psp VerilogHDL_counter\dispselect\db\dispselect.rtlv.hdb VerilogHDL_counter\dispselect\db\dispselect.rtlv_sg.cdb VerilogHDL_counter\dispselect\db\dispselect.rtlv_sg_swap.cdb VerilogHDL_counter\dispselect\db\dispselect.sgdiff.cdb VerilogHDL_counter\dispselect\db\dispselect.sgdiff.hdb VerilogHDL_counter\dispselect\db\dispselect.sim.hdb VerilogHDL_counter\dispselect\db\dispselect.sim.qmsg VerilogHDL_counter\dispselect\db\dispselect.sim.rdb VerilogHDL_counter\dispselect\db\dispselect.sim.vwf VerilogHDL_counter\dispselect\db\dispselect.sld_design_entry.sci VerilogHDL_counter\dispselect\db\dispselect.sld_design_entry_dsc.sci VerilogHDL_counter\dispselect\db\dispselect.syn_hier_info VerilogHDL_counter\dispselect\db\dispselect.tan.qmsg VerilogHDL_counter\dispselect\db\dispselect_cmp.qrpt VerilogHDL_counter\dispselect\db\dispselect_sim.qrpt VerilogHDL_counter\dispselect\dispselect.asm.rpt VerilogHDL_counter\dispselect\dispselect.bsf VerilogHDL_counter\dispselect\dispselect.done VerilogHDL_counter\dispselect\dispselect.fit.eqn VerilogHDL_counter\dispselect\dispselect.fit.rpt VerilogHDL_counter\dispselect\dispselect.fit.summary VerilogHDL_counter\dispselect\dispselect.flow.rpt VerilogHDL_counter\dispselect\dispselect.map.eqn VerilogHDL_counter\dispselect\dispselect.map.rpt VerilogHDL_counter\dispselect\dispselect.map.summary VerilogHDL_counter\dispselect\dispselect.pin VerilogHDL_counter\dispselect\dispselect.pof VerilogHDL_counter\dispselect\dispselect.qpf VerilogHDL_counter\dispselect\dispselect.qsf VerilogHDL_counter\dispselect\dispselect.qws VerilogHDL_counter\dispselect\dispselect.sim.rpt VerilogHDL_counter\dispselect\dispselect.tan.rpt VerilogHDL_counter\dispselect\dispselect.tan.summary VerilogHDL_counter\dispselect\dispselect.v VerilogHDL_counter\dispselect\dispselect.vwf VerilogHDL_counter\fdiv\cmp_state.ini VerilogHDL_counter\fdiv\db\fdiv.(0).cnf.cdb VerilogHDL_counter\fdiv\db\fdiv.(0).cnf.hdb VerilogHDL_counter\fdiv\db\fdiv.(1).cnf.cdb VerilogHDL_counter\fdiv\db\fdiv.(1).cnf.hdb VerilogHDL_counter\fdiv\db\fdiv.(2).cnf.cdb VerilogHDL_counter\fdiv\db\fdiv.(2).cnf.hdb VerilogHDL_counter\fdiv\db\fdiv.asm.qmsg VerilogHDL_counter\fdiv\db\fdiv.cmp.cdb VerilogHDL_counter\fdiv\db\fdiv.cmp.ddb VerilogHDL_counter\fdiv\db\fdiv.cmp.hdb VerilogHDL_counter\fdiv\db\fdiv.cmp.rdb VerilogHDL_counter\fdiv\db\fdiv.cmp.tdb VerilogHDL_counter\fdiv\db\fdiv.cmp0.ddb VerilogHDL_counter\fdiv\db\fdiv.db_info VerilogHDL_counter\fdiv\db\fdiv.eco.cdb VerilogHDL_counter\fdiv\db\fdiv.eds_overflow VerilogHDL_counter\fdiv\db\fdiv.fit.qmsg VerilogHDL_counter\fdiv\db\fdiv.hier_info VerilogHDL_counter\fdiv\db\fdiv.hif VerilogHDL_counter\fdiv\db\fdiv.map.cdb VerilogHDL_counter\fdiv\db\fdiv.map.hdb VerilogHDL_counter\fdiv\db\fdiv.map.qmsg VerilogHDL_counter\fdiv\db\fdiv.pre_map.cdb VerilogHDL_counter\fdiv\db\fdiv.pre_map.hdb VerilogHDL_counter\fdiv\db\fdiv.psp VerilogHDL_counter\fdiv\db\fdiv.rtlv.hdb VerilogHDL_counter\fdiv\db\fdiv.rtlv_sg.cdb VerilogHDL_counter\fdiv\db\fdiv.rtlv_sg_swap.cdb VerilogHDL_counter\fdiv\db\fdiv.sgdiff.cdb VerilogHDL_counter\fdiv\db\fdiv.sgdiff.hdb VerilogHDL_counter\fdiv\db\fdiv.sim.hdb VerilogHDL_counter\fdiv\db\fdiv.sim.qmsg VerilogHDL_counter\fdiv\db\fdiv.sim.rdb VerilogHDL_counter\fdiv\db\fdiv.sim.vwf VerilogHDL_counter\fdiv\db\fdiv.sld_design_entry.sci VerilogHDL_counter\fdiv\db\fdiv.sld_design_entry_dsc.sci VerilogHDL_counter\fdiv\db\fdiv.syn_hier_info VerilogHDL_counter\fdiv\db\fdiv.tan.qmsg VerilogHDL_counter\fdiv\db\fdiv_cmp.qrpt VerilogHDL_counter\fdiv\db\fdiv_sim.qrpt VerilogHDL_counter\fdiv\fdiv.asm.rpt VerilogHDL_counter\fdiv\fdiv.bsf VerilogHDL_counter\fdiv\fdiv.done VerilogHDL_counter\fdiv\fdiv.fit.eqn VerilogHDL_counter\fdiv\fdiv.fit.rpt VerilogHDL_counter\fdiv\fdiv.fit.summary VerilogHDL_counter\fdiv\fdiv.flow.rpt VerilogHDL_counter\fdiv\fdiv.map.eqn VerilogHDL_counter\fdiv\fdiv.map.rpt VerilogHDL_counter\fdiv\fdiv.map.summary VerilogHDL_counter\fdiv\fdiv.pin VerilogHDL_counter\fdiv\fdiv.pof VerilogHDL_counter\fdiv\fdiv.qpf VerilogHDL_counter\fdiv\fdiv.qsf VerilogHDL_counter\fdiv\fdiv.qws VerilogHDL_counter\fdiv\fdiv.sim.rpt VerilogHDL_counter\fdiv\fdiv.tan.rpt VerilogHDL_counter\fdiv\fdiv.tan.summary VerilogHDL_counter\fdiv\fdiv.v VerilogHDL_counter\fdiv\fdiv.vwf VerilogHDL_counter\flip_latch\cmp_state.ini VerilogHDL_counter\flip_latch\db\flip_latch.(0).cnf.cdb VerilogHDL_counter\flip_latch\db\flip_latch.(0).cnf.hdb VerilogHDL_counter\flip_latch\db\flip_latch.asm.qmsg VerilogHDL_counter\flip_latch\db\flip_latch.cmp.cdb VerilogHDL_counter\flip_latch\db\flip_latch.cmp.ddb VerilogHDL_counter\flip_latch\db\flip_latch.cmp.hdb VerilogHDL_counter\flip_latch\db\flip_latch.cmp.rdb VerilogHDL_counter\flip_latch\db\flip_latch.cmp.tdb VerilogHDL_counter\flip_latch\db\flip_latch.cmp0.ddb VerilogHDL_counter\flip_latch\db\flip_latch.db_info VerilogHDL_counter\flip_latch\db\flip_latch.eco.cdb VerilogHDL_counter\flip_latch\db\flip_latch.eds_overflow VerilogHDL_counter\flip_latch\db\flip_latch.fit.qmsg VerilogHDL_counter\flip_latch\db\flip_latch.hier_info VerilogHDL_counter\flip_latch\db\flip_latch.hif VerilogHDL_counter\flip_latch\db\flip_latch.map.cdb VerilogHDL_counter\flip_latch\db\flip_latch.map.hdb VerilogHDL_counter\flip_latch\db\flip_latch.map.qmsg VerilogHDL_counter\flip_latch\db\flip_latch.pre_map.cdb VerilogHDL_counter\flip_latch\db\flip_latch.pre_map.hdb VerilogHDL_counter\flip_latch\db\flip_latch.psp VerilogHDL_counter\flip_latch\db\flip_latch.rtlv.hdb VerilogHDL_counter\flip_latch\db\flip_latch.rtlv_sg.cdb VerilogHDL_counter\flip_latch\db\flip_latch.rtlv_sg_swap.cdb VerilogHDL_counter\flip_latch\db\flip_latch.sgdiff.cdb VerilogHDL_counter\flip_latch\db\flip_latch.sgdiff.hdb VerilogHDL_counter\flip_latch\db\flip_latch.sim.hdb VerilogHDL_counter\flip_latch\db\flip_latch.sim.qmsg VerilogHDL_counter\flip_latch\db\flip_latch.sim.rdb VerilogHDL_counter\flip_latch\db\flip_latch.sim.vwf VerilogHDL_counter\flip_latch\db\flip_latch.sld_design_entry.sci VerilogHDL_counter\flip_latch\db\flip_latch.sld_design_entry_dsc.sci VerilogHDL_counter\flip_latch\db\flip_latch.syn_hier_info VerilogHDL_counter\flip_latch\db\flip_latch.tan.qmsg VerilogHDL_counter\flip_latch\db\flip_latch_cmp.qrpt VerilogHDL_counter\flip_latch\db\flip_latch_sim.qrpt VerilogHDL_counter\flip_latch\flip_latch.asm.rpt VerilogHDL_counter\flip_latch\flip_latch.bsf VerilogHDL_counter\flip_latch\flip_latch.done VerilogHDL_counter\flip_latch\flip_latch.fit.eqn VerilogHDL_counter\flip_latch\flip_latch.fit.rpt VerilogHDL_counter\flip_latch\flip_latch.fit.summary VerilogHDL_counter\flip_latch\flip_latch.flow.rpt VerilogHDL_counter\flip_latch\flip_latch.map.eqn VerilogHDL_counter\flip_latch\flip_latch.map.rpt VerilogHDL_counter\flip_latch\flip_latch.map.summary VerilogHDL_counter\flip_latch\flip_latch.pin VerilogHDL_counter\flip_latch\flip_latch.pof VerilogHDL_counter\flip_latch\flip_latch.qpf VerilogHDL_counter\flip_latch\flip_latch.qsf VerilogHDL_counter\flip_latch\flip_latch.qws VerilogHDL_counter\flip_latch\flip_latch.sim.rpt VerilogHDL_counter\flip_latch\flip_latch.tan.rpt VerilogHDL_counter\flip_latch\flip_latch.tan.summary VerilogHDL_counter\flip_latch\flip_latch.v VerilogHDL_counter\flip_latch\flip_latch.vwf VerilogHDL_counter\gate_control\cmp_state.ini VerilogHDL_counter\gate_control\db\gate_control.(0).cnf.cdb VerilogHDL_counter\gate_control\db\gate_control.(0).cnf.hdb VerilogHDL_counter\gate_control\db\gate_control.asm.qmsg VerilogHDL_counter\gate_control\db\gate_control.cmp.cdb VerilogHDL_counter\gate_control\db\gate_control.cmp.ddb VerilogHDL_counter\gate_control\db\gate_control.cmp.hdb VerilogHDL_counter\gate_control\db\gate_control.cmp.rdb VerilogHDL_counter\gate_control\db\gate_control.cmp.tdb VerilogHDL_counter\gate_control\db\gate_control.cmp0.ddb VerilogHDL_counter\gate_control\db\gate_control.db_info VerilogHDL_counter\gate_control\db\gate_control.eco.cdb VerilogHDL_counter\gate_control\db\gate_control.eds_overflow VerilogHDL_counter\gate_control\db\gate_control.fit.qmsg VerilogHDL_counter\gate_control\db\gate_control.hier_info VerilogHDL_counter\gate_control\db\gate_control.hif VerilogHDL_counter\gate_control\db\gate_control.map.cdb VerilogHDL_counter\gate_control\db\gate_control.map.hdb VerilogHDL_counter\gate_control\db\gate_control.map.qmsg VerilogHDL_counter\gate_control\db\gate_control.pre_map.cdb VerilogHDL_counter\gate_control\db\gate_control.pre_map.hdb VerilogHDL_counter\gate_control\db\gate_control.psp VerilogHDL_counter\gate_control\db\gate_control.rtlv.hdb VerilogHDL_counter\gate_control\db\gate_control.rtlv_sg.cdb VerilogHDL_counter\gate_control\db\gate_control.rtlv_sg_swap.cdb VerilogHDL_counter\gate_control\db\gate_control.sgdiff.cdb VerilogHDL_counter\gate_control\db\gate_control.sgdiff.hdb VerilogHDL_counter\gate_control\db\gate_control.sim.hdb VerilogHDL_counter\gate_control\db\gate_control.sim.qmsg VerilogHDL_counter\gate_control\db\gate_control.sim.rdb VerilogHDL_counter\gate_control\db\gate_control.sim.vwf VerilogHDL_counter\gate_control\db\gate_control.sld_design_entry.sci VerilogHDL_counter\gate_control\db\gate_control.sld_design_entry_dsc.sci VerilogHDL_counter\gate_control\db\gate_control.syn_hier_info VerilogHDL_counter\gate_control\db\gate_control.tan.qmsg VerilogHDL_counter\gate_control\db\gate_control_cmp.qrpt VerilogHDL_counter\gate_control\db\gate_control_sim.qrpt VerilogHDL_counter\gate_control\gate_control.asm.rpt VerilogHDL_counter\gate_control\gate_control.bsf VerilogHDL_counter\gate_control\gate_control.done VerilogHDL_counter\gate_control\gate_control.fit.eqn VerilogHDL_counter\gate_control\gate_control.fit.rpt VerilogHDL_counter\gate_control\gate_control.fit.summary VerilogHDL_counter\gate_control\gate_control.flow.rpt VerilogHDL_counter\gate_control\gate_control.map.eqn VerilogHDL_counter\gate_control\gate_control.map.rpt VerilogHDL_counter\gate_control\gate_control.map.summary VerilogHDL_counter\gate_control\gate_control.pin VerilogHDL_counter\gate_control\gate_control.pof VerilogHDL_counter\gate_control\gate_control.qpf VerilogHDL_counter\gate_control\gate_control.qsf VerilogHDL_counter\gate_control\gate_control.qws VerilogHDL_counter\gate_control\gate_control.sim.rpt VerilogHDL_counter\gate_control\gate_control.tan.rpt VerilogHDL_counter\gate_control\gate_control.tan.summary VerilogHDL_counter\gate_control\gate_control.v VerilogHDL_counter\gate_control\gate_control.vwf VerilogHDL_counter\main\cmp_state.ini VerilogHDL_counter\main\counter.v VerilogHDL_counter\main\data_mux.v VerilogHDL_counter\main\db\main.(0).cnf.cdb VerilogHDL_counter\main\db\main.(0).cnf.hdb VerilogHDL_counter\main\db\main.(1).cnf.cdb VerilogHDL_counter\main\db\main.(1).cnf.hdb VerilogHDL_counter\main\db\main.(10).cnf.cdb VerilogHDL_counter\main\db\main.(10).cnf.hdb VerilogHDL_counter\main\db\main.(2).cnf.cdb VerilogHDL_counter\main\db\main.(2).cnf.hdb VerilogHDL_counter\main\db\main.(3).cnf.cdb VerilogHDL_counter\main\db\main.(3).cnf.hdb VerilogHDL_counter\main\db\main.(4).cnf.cdb VerilogHDL_counter\main\db\main.(4).cnf.hdb VerilogHDL_counter\main\db\main.(5).cnf.cdb VerilogHDL_counter\main\db\main.(5).cnf.hdb VerilogHDL_counter\main\db\main.(6).cnf.cdb VerilogHDL_counter\main\db\main.(6).cnf.hdb VerilogHDL_counter\main\db\main.(7).cnf.cdb VerilogHDL_counter\main\db\main.(7).cnf.hdb VerilogHDL_counter\main\db\main.(8).cnf.cdb VerilogHDL_counter\main\db\main.(8).cnf.hdb VerilogHDL_counter\main\db\main.(9).cnf.cdb VerilogHDL_counter\main\db\main.(9).cnf.hdb VerilogHDL_counter\main\db\main.asm.qmsg VerilogHDL_counter\main\db\main.cmp.cdb VerilogHDL_counter\main\db\main.cmp.ddb VerilogHDL_counter\main\db\main.cmp.hdb VerilogHDL_counter\main\db\main.cmp.rdb VerilogHDL_counter\main\db\main.cmp.tdb VerilogHDL_counter\main\db\main.cmp0.ddb VerilogHDL_counter\main\db\main.db_info VerilogHDL_counter\main\db\main.eco.cdb VerilogHDL_counter\main\db\main.eds_overflow VerilogHDL_counter\main\db\main.fit.qmsg VerilogHDL_counter\main\db\main.hier_info VerilogHDL_counter\main\db\main.hif VerilogHDL_counter\main\db\main.map.cdb VerilogHDL_counter\main\db\main.map.hdb VerilogHDL_counter\main\db\main.map.qmsg VerilogHDL_counter\main\db\main.pre_map.cdb VerilogHDL_counter\main\db\main.pre_map.hdb VerilogHDL_counter\main\db\main.psp VerilogHDL_counter\main\db\main.rtlv.hdb VerilogHDL_counter\main\db\main.rtlv_sg.cdb VerilogHDL_counter\main\db\main.rtlv_sg_swap.cdb VerilogHDL_counter\main\db\main.sgdiff.cdb VerilogHDL_counter\main\db\main.sgdiff.hdb VerilogHDL_counter\main\db\main.sim.hdb VerilogHDL_counter\main\db\main.sim.qmsg VerilogHDL_counter\main\db\main.sim.rdb VerilogHDL_counter\main\db\main.sim.vwf VerilogHDL_counter\main\db\main.sld_design_entry.sci VerilogHDL_counter\main\db\main.sld_design_entry_dsc.sci VerilogHDL_counter\main\db\main.syn_hier_info VerilogHDL_counter\main\db\main.tan.qmsg VerilogHDL_counter\main\db\main_cmp.qrpt VerilogHDL_counter\main\db\main_sim.qrpt VerilogHDL_counter\main\dispdecoder.v VerilogHDL_counter\main\dispselect.v VerilogHDL_counter\main\fdiv.v VerilogHDL_counter\main\flip_latch.v VerilogHDL_counter\main\gate_control.v VerilogHDL_counter\main\main.asm.rpt VerilogHDL_counter\main\main.bdf VerilogHDL_counter\main\main.done VerilogHDL_counter\main\main.fit.eqn VerilogHDL_counter\main\main.fit.rpt VerilogHDL_counter\main\main.fit.summary VerilogHDL_counter\main\main.flow.rpt VerilogHDL_counter\main\main.map.eqn VerilogHDL_counter\main\main.map.rpt VerilogHDL_counter\main\main.map.summary VerilogHDL_counter\main\main.pin VerilogHDL_counter\main\main.pof VerilogHDL_counter\main\main.qpf VerilogHDL_counter\main\main.qsf VerilogHDL_counter\main\main.qws VerilogHDL_counter\main\main.sim.rpt VerilogHDL_counter\main\main.tan.rpt VerilogHDL_counter\main\main.tan.summary VerilogHDL_counter\main\main.v VerilogHDL_counter\main\main.vwf VerilogHDL_counter\counter\db VerilogHDL_counter\data_mux\db VerilogHDL_counter\dispdecoder\db VerilogHDL_counter\dispselect\db VerilogHDL_counter\fdiv\db VerilogHDL_counter\flip_latch\db VerilogHDL_counter\gate_control\db VerilogHDL_counter\main\db VerilogHDL_counter\counter VerilogHDL_counter\data_mux VerilogHDL_counter\dispdecoder VerilogHDL_counter\dispselect VerilogHDL_counter\fdiv VerilogHDL_counter\flip_latch VerilogHDL_counter\gate_control VerilogHDL_counter\main VerilogHDL_counter