文件名称:uart_rx
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actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
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压缩包 : 61549822uart_rx.rar 列表 uart_rx uart_rx\uart_rx.prj uart_rx\viewdraw uart_rx\viewdraw\wir uart_rx\viewdraw\vf uart_rx\viewdraw\vf\project.lst uart_rx\viewdraw\sym uart_rx\viewdraw\sch uart_rx\viewdraw\viewdraw.ini uart_rx\synthesis uart_rx\synthesis\.recordref uart_rx\synthesis\rcvr.areasrr uart_rx\synthesis\rcvr.edn uart_rx\synthesis\rcvr.map uart_rx\synthesis\rcvr.sdf uart_rx\synthesis\rcvr.srd uart_rx\synthesis\rcvr.srm uart_rx\synthesis\rcvr.srr uart_rx\synthesis\rcvr.srs uart_rx\synthesis\rcvr.tlg uart_rx\synthesis\rcvr_sdc.sdc uart_rx\synthesis\stdout.log uart_rx\synthesis\traplog.tlg uart_rx\synthesis\syntmp uart_rx\synthesis\syntmp\rcvr.msg uart_rx\synthesis\syntmp\rcvr.plg uart_rx\synthesis\rcvr_syn.prj uart_rx\stimulus uart_rx\smartgen uart_rx\smartgen\smartgen.aws uart_rx\simulation uart_rx\simulation\modelsim.ini.sav uart_rx\simulation\modelsim.ini uart_rx\simulation\meminit.dat uart_rx\phy_synthesis uart_rx\hdl uart_rx\hdl\rcvr.v uart_rx\hdl\waveperl.log uart_rx\designer uart_rx\designer\impl1 uart_rx\designer\impl1\designer.log uart_rx\designer\impl1\rcvr.adb uart_rx\designer\impl1\rcvr.ide_des uart_rx\designer\impl1\rcvr.stp uart_rx\designer\impl1\rcvr.tcl uart_rx\designer\impl1\simulation uart_rx\designer\impl1\rcvr_fp uart_rx\designer\impl1\rcvr_fp\rcvr.pro uart_rx\designer\impl1\rcvr.dtf uart_rx\designer\impl1\rcvr.dtf\verify.log uart_rx\designer\impl1\ada00192-1.tmp uart_rx\designer\impl1\ada00192-3.tmp uart_rx\designer\impl1\rcvr_1_fp uart_rx\designer\impl1\rcvr_1_fp\rcvr.pro uart_rx\designer\impl1\rcvr_1_fp\$$FlashPro_FPBBALTLPT1.L$$ uart_rx\designer\impl1\rcvr_1_fp\rcvr.log uart_rx\designer\impl1\rcvr_1.ide_des uart_rx\designer\impl1\unsav.lok uart_rx\designer\impl1\assert.log uart_rx\designer\impl1\ada00552-3.tmp uart_rx\designer\impl1\ada00552-5.tmp uart_rx\designer\impl1\rcvr.lok uart_rx\designer\impl1\ada01764-2.tmp uart_rx\designer\impl1\ada01764-4.tmp uart_rx\designer\impl1\unsav001.lok uart_rx\coreconsole uart_rx\constraint uart_rx\uart_rx.prj.convert.7.3.bak uart_rx\component