文件名称:verilog_code
介绍说明－－下载内容均来自于网络，请自行研究使用
這是一堆verilog的source code.包含許多常用的小電路.還不錯用.-many verilog source codes, include a lot of small electrocircuit.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 492928verilog_code.rar 列表 VERILOG_CODE VERILOG_CODE\ADD_BEH.V VERILOG_CODE\ADD_RTL.V VERILOG_CODE\ADD_SIM.V VERILOG_CODE\AFIFO.ACF VERILOG_CODE\AFIFO.HIF VERILOG_CODE\AFIFO.MMF VERILOG_CODE\AFIFO.V VERILOG_CODE\AFIFO_BEH.V VERILOG_CODE\AFIFO_RTL.ACF VERILOG_CODE\AFIFO_RTL.HIF VERILOG_CODE\AFIFO_RTL.MMF VERILOG_CODE\AFIFO_RTL.V VERILOG_CODE\AFIFO_SIM.V VERILOG_CODE\CHECKSUM.V VERILOG_CODE\CHECK_SIM.V VERILOG_CODE\CNT_BEH.V VERILOG_CODE\CNT_RTL.V VERILOG_CODE\CNT_SIM.V VERILOG_CODE\CRC_BEH.V VERILOG_CODE\CRC_RTL.V VERILOG_CODE\CRC_SIM.V VERILOG_CODE\DRAMCON_BEH.V VERILOG_CODE\DRAMCON_RTL.V VERILOG_CODE\DRAMCON_SIM.V VERILOG_CODE\DUAL.V VERILOG_CODE\DUAL_SIM.V VERILOG_CODE\ENCR-RTL.ACF VERILOG_CODE\ENCR-RTL.HIF VERILOG_CODE\ENCR-RTL.V VERILOG_CODE\ENCRYPTATION.ACF VERILOG_CODE\ENCRYPTATION.CNF VERILOG_CODE\ENCRYPTATION.FIT VERILOG_CODE\ENCRYPTATION.HEX VERILOG_CODE\ENCRYPTATION.HIF VERILOG_CODE\ENCRYPTATION.MMF VERILOG_CODE\ENCRYPTATION.NDB VERILOG_CODE\ENCRYPTATION.PIN VERILOG_CODE\ENCRYPTATION.POF VERILOG_CODE\ENCRYPTATION.RPT VERILOG_CODE\ENCRYPTATION.SNF VERILOG_CODE\ENCRYPTATION.SOF VERILOG_CODE\ENCRYPTATION.TTF VERILOG_CODE\ENCRYPTATION.V VERILOG_CODE\ENCRYPTATION(1).CNF VERILOG_CODE\ENCR_BEH.V VERILOG_CODE\ENCR_RTL.ACF VERILOG_CODE\ENCR_RTL.HIF VERILOG_CODE\ENCR_RTL.MMF VERILOG_CODE\ENCR_RTL.V VERILOG_CODE\ENCR_SIM.V VERILOG_CODE\FPDRAMCON_BEH.V VERILOG_CODE\FPDRAMCON_RTL.V VERILOG_CODE\FULLCASE.V VERILOG_CODE\FULLCASE1.V VERILOG_CODE\FULLCASE2.V VERILOG_CODE\HAMDEC.V VERILOG_CODE\HAMGEN.V VERILOG_CODE\HAM_SIM.V VERILOG_CODE\JK_BEH.V VERILOG_CODE\JK_RTL.V VERILOG_CODE\JK_SIM.V VERILOG_CODE\LFSR2_BEH.V VERILOG_CODE\LFSR2_RTL.V VERILOG_CODE\LFSR_BEH.V VERILOG_CODE\LFSR_RTL.V VERILOG_CODE\LFSR_SIM.V VERILOG_CODE\LIB.DLS VERILOG_CODE\MEALY_BEH.V VERILOG_CODE\MEALY_RTL.V VERILOG_CODE\MONO.V VERILOG_CODE\MONO2.V VERILOG_CODE\MONO_SIM.V VERILOG_CODE\MOORE2_RTL.V VERILOG_CODE\MOORE_BEH.V VERILOG_CODE\MOORE_RTL.V VERILOG_CODE\NORACE.V VERILOG_CODE\ONEHOT_RTL.V VERILOG_CODE\OPT.V VERILOG_CODE\PAR.V VERILOG_CODE\PAR_SIM.V VERILOG_CODE\PLL_BEH.V VERILOG_CODE\PLL_RTL.V VERILOG_CODE\PLL_SIM.V VERILOG_CODE\RAM.V VERILOG_CODE\RAM_SIM.V VERILOG_CODE\SFIFO_BEH.V VERILOG_CODE\SFIFO_RTL.V VERILOG_CODE\SFIFO_SIM.V VERILOG_CODE\SHIFT_BEH.V VERILOG_CODE\SHIFT_RTL.V VERILOG_CODE\SHIFT_SIM.V VERILOG_CODE\SMULTIPLY1_RTL.V VERILOG_CODE\SMULTIPLY2_RTL.V VERILOG_CODE\SMULTIPLY3_RTL.V VERILOG_CODE\SMULTIPLY_BEH.V VERILOG_CODE\SMULTIPLY_SIM.V VERILOG_CODE\SM_ROM.V VERILOG_CODE\SRAMCON_BEH.V VERILOG_CODE\SRAMCON_RTL.V VERILOG_CODE\SRAMCON_SIM.V VERILOG_CODE\SSRAMCON_BEH.V VERILOG_CODE\SSRAMCON_RTL.V VERILOG_CODE\SSRAMCON_SIM.V VERILOG_CODE\STATE_SIM.V VERILOG_CODE\TEMPLATE.V VERILOG_CODE\U1942304.DLS VERILOG_CODE\U2050358.DLS VERILOG_CODE\U8414017.DLS VERILOG_CODE\U8569794.DLS VERILOG_CODE\UMULTIPLY1_RTL.V VERILOG_CODE\UMULTIPLY2_RTL.V VERILOG_CODE\UMULTIPLY3_RTL.V VERILOG_CODE\UMULTIPLY_BEH.V VERILOG_CODE\UMULTIPLY_SIM.V VERILOG_CODE\UM_ROM.V VERILOG_CODE\VERILOG SOURCE CODE1.V VERILOG_CODE\TIMING VERILOG_CODE\TIMING\WORK VERILOG_CODE\TIMING\WORK\MODELSIM.INI VERILOG_CODE\TIMING\WORK\_INFO VERILOG_CODE\TIMING\SRC VERILOG_CODE\TIMING\SRC\RAM VERILOG_CODE\TIMING\SRC\RAM\DEFAULT_VIEW VERILOG_CODE\TIMING\SRC\RAM\RAM.V VERILOG_CODE\TIMING\SRC\RAM\SYMBOL.SB VERILOG_CODE\TIMING\SRC\INTRA_ASSIGNMENT VERILOG_CODE\TIMING\SRC\INTRA_ASSIGNMENT\DEFAULT_VIEW VERILOG_CODE\TIMING\SRC\INTRA_ASSIGNMENT\INTRA_ASSIGNMENT.V VERILOG_CODE\TIMING\SRC\INTRA_ASSIGNMENT\SYMBOL.SB VERILOG_CODE\TIMING\SRC\INTRA_ASSIGNMENT\INTRA_ASSIGNMENT.V.INFO VERILOG_CODE\TIMING\SRC\INTRA_ASSIGNMENT\INTRA_ASSIGNMENT.V.INFO\STRUCTURE.DH VERILOG_CODE\TIMING\SRC\.XRF VERILOG_CODE\TIMING\SRC\.XRF\INTRA_ASSIGNMENT.XRF VERILOG_CODE\TIMING\SRC\.XRF\RAM.XRF VERILOG_CODE\TIMING\LS VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\XDB VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\SCRIPTS VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\SCRIPTS\OPEN_FILES.TCL VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\SCRIPTS\OPTIMIZE.TCL VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\SCRIPTS\SETUP.TCL VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\SCRIPTS\SPECTRUM.TCL VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\REPORTS VERILOG_CODE\TIMING\LS\INTRA_ASSIGNMENT_INTRA_ASSIGNMENT\NETLISTS VERILOG_CODE\TIMING\HDL VERILOG_CODE\TIMING\HDL\INTRA_ASSIGNMENT.V VERILOG_CODE\TIMING\HDL\RAM.V