文件名称:fen
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verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2
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下载文件列表
压缩包 : 857425fen.rar 列表 fen fen\fen.npl fen\fen.v fen\fen.dhp fen\fen_map.ngm fen\__projnav.log fen\automake.log fen\fen_test.v fen\fen.bld fen\fen.ngd fen\fen_fen_test_v_tf.udo fen\fen_fen_test_v_tf.fdo fen\transcript fen\vsim.wlf fen\fen.prj fen\fen.par fen\fen.cmd_log fen\fen.syr fen\fen.ncd fen\fen_vhdl.prj fen\fen.lso fen\fen.xlate_nlf fen\fen.ngr fen\fen_map.ncd fen\fen.pcf fen\fen.ngc fen\fen.stx fen\fen_translate.nlf fen\fen.nc1 fen\.untf fen\fen.ucf fen\fen.xpi fen\fen.lfp fen\_pace.ucf fen\fen_pad.csv fen\fen.pad fen\fen.ucf.untf fen\fen_translate.v fen\fen.versim_xlate fen\fen_last_par.ncd fen\fen_pad.txt fen\fen.ngm fen\fen.placed_ncd_tracker fen\fen.routed_ncd_tracker fen\fen.twr fen\fen.twx fen\fen.bgn fen\fen.drc fen\fen.bit fen\_impact.log fen\_impact.cmd fen\CC.mcs fen\AB.mcs fen\fen.pad_txt fen\AB.prm fen\AB.sig fen\fen_map.nlf fen\fen_map.sdf fen\fen.ut fen\bitgen.ut fen\fen_fen_test_v_tf.ndo fen\fen_map.v fen\fen.versim_map fen\fen.map_nlf fen\fen_fen_test_v_tf.mdo fen\fen_timesim.nlf fen\fen_timesim.sdf fen\fen_timesim.v fen\dd.mcs fen\coregen.log fen\coregen.prj fen\fen.versim_par fen\fen.par_nlf fen\fen_fen_test_v_tf.tdo fen\CC.prm fen\CC.sig fen\fen.mrp fen\dd.prm fen\dd.sig fen\_ngo fen\_ngo\netlist.lst fen\xst fen\xst\work fen\xst\work\hdllib.ref fen\xst\work\vlg5D fen\xst\work\vlg5D\fen.bin fen\work fen\work\_info fen\work\glbl fen\work\glbl\_primary.vhd fen\work\glbl\verilog.psm fen\work\glbl\_primary.dat fen\work\fen_fen_test_v_tf fen\work\fen_fen_test_v_tf\_primary.vhd fen\work\fen_fen_test_v_tf\verilog.psm fen\work\fen_fen_test_v_tf\_primary.dat fen\work\fen fen\work\fen\_primary.vhd fen\work\fen\verilog.psm fen\work\fen\_primary.dat fen\__projnav fen\__projnav\createTF.err fen\__projnav\fen.gfl fen\__projnav\runXst_tcl.rsp fen\__projnav\fen_flowplus.gfl fen\__projnav\fen.xst fen\__projnav\parentEditConstraintsTextApp_tcl.rsp fen\__projnav\parentAssignPackagePinsApp_tcl.rsp fen\__projnav\ednTOngd_tcl.rsp fen\__projnav\nc1TOncd_tcl.rsp fen\__projnav\posttrc.log fen\__projnav\fen_ncdTOut_tcl.rsp fen\__projnav\bitgen.rsp fen\__projnav\coregen.rsp fen\__projnav\netgen_map_tcl.rsp fen\__projnav\parentCreateAreaConstraintsApp_tcl.rsp fen\__projnav\xlateFloorPlanner.rsp fen\__projnav\netgen_par_tcl.rsp fen\__projnav\map.log fen\__projnav\par.log