压缩包 : 755570verilog_book.rar 列表
VERILOG_BOOK_EXAMPLES
VERILOG_BOOK_EXAMPLES\APPA
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\MUX.SPJ
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\MUX.V
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRI0.SPJ
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRI0.V
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRIREG.SPJ
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\TRIREG.V
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\WAND_WOR.SPJ
VERILOG_BOOK_EXAMPLES\APPA\CHAP_EG\WAND_WOR.V
VERILOG_BOOK_EXAMPLES\APPA\README.TXT
VERILOG_BOOK_EXAMPLES\APPB
VERILOG_BOOK_EXAMPLES\APPB\README.TXT
VERILOG_BOOK_EXAMPLES\APPC
VERILOG_BOOK_EXAMPLES\APPC\README.TXT
VERILOG_BOOK_EXAMPLES\APPD
VERILOG_BOOK_EXAMPLES\APPD\README.TXT
VERILOG_BOOK_EXAMPLES\APPE
VERILOG_BOOK_EXAMPLES\APPE\README.TXT
VERILOG_BOOK_EXAMPLES\APPF
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO\FIFO.SPJ
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO\FIFO.V
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\FIFO\README.TXT
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\DRAM.SPJ
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\DRAM.TIM
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\DRAM.V
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\INI_FILE
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\README.TXT
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\RAM\TESTDRAM.V
VERILOG_BOOK_EXAMPLES\APPF\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\APPF\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP1
VERILOG_BOOK_EXAMPLES\CHAP1\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP10
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\DIST-DEL.V
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\DIST_DEL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\FULL-CON.V
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\FULL_CON.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\LUMP-DEL.V
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\LUMP_DEL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\PATH-DEL.V
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\PATH_DEL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\SDPD.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\CHAP_EG\SDPD.V
VERILOG_BOOK_EXAMPLES\CHAP10\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP10\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP10\EXERCISE\EX3.SPJ
VERILOG_BOOK_EXAMPLES\CHAP10\EXERCISE\EX3.V
VERILOG_BOOK_EXAMPLES\CHAP10\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP11
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\CFF.SPJ
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\CFF.V
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\MUX.SPJ
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\MUX.V
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\NOR.SPJ
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\NOR.V
VERILOG_BOOK_EXAMPLES\CHAP11\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP11\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP11\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP11\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP11\EXERCISE\EX2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP11\EXERCISE\EX2.V
VERILOG_BOOK_EXAMPLES\CHAP11\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP12
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\DFF.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\DFF.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\DFFSHORT.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\DFFSHORT.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\FULLADD.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\FULLADD.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\LATCH.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\LATCH.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\MUX4_1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\MUX4_1.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\TFF_CNTR.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\TFF_CNTR.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\UDP_AND.V
VERILOG_BOOK_EXAMPLES\CHAP12\CHAP_EG\UDP_OR.V
VERILOG_BOOK_EXAMPLES\CHAP12\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP12\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP12\EXERCISE\EX2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP12\EXERCISE\EX2.V
VERILOG_BOOK_EXAMPLES\CHAP12\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\CR_VLOG
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\GET_PORT
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\GET_PORT\GET_PORT.C
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\GET_PORT\GET_PORT.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\GET_PORT\MUX.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\GET_PORT\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\MY_MON
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\MY_MON\MUX.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\MY_MON\MY_MON.C
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\MY_MON\MY_MON.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\MY_MON\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\STOP_FIN
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\STOP_FIN\MUX.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\STOP_FIN\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\STOP_FIN\STOP_FIN.C
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\STOP_FIN\STOP_FIN.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\EXAMPLES\VERIUSER.C
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\HELLO_WD
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\HELLO_WD\CR_VLOG
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\HELLO_WD\HELLO.V
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\HELLO_WD\HELLO_V.C
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\HELLO_WD\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\HELLO_WD\VERIUSER.C
VERILOG_BOOK_EXAMPLES\CHAP13\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\CR_VLOG
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\EX1
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\EX1\GET_PORT.C
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\EX1\GET_PORT.V
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\EX1\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP13\EXERCISE\VERIUSER.C
VERILOG_BOOK_EXAMPLES\CHAP13\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP14
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\EDGE_DFF.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\EDGE_DFF.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\FADDER.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\FADDER.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\FOR.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\FOR.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\FUNCTION.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\FUNCTION.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\LATCH.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\LATCH.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\LATCHMUX.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\LATCHMUX.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\MULTIPLE.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\MULTIPLE.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\MUX.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\MUX.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\ABC_100.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\GATE.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\MAG_COMP.GV
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\MAG_COMP.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\RTL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\MAG_COMP\STIMULUS.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\ABC_100.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\GATE.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\RTL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\VEND.GV
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\VEND.V
VERILOG_BOOK_EXAMPLES\CHAP14\CHAP_EG\VENDING\VENDTEST.V
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\ABC_100.V
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\CLOOKAHD.GV
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\CLOOKAHD.V
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\GATE.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\RTL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP14\EXERCISE\EX1\STIMULUS.V
VERILOG_BOOK_EXAMPLES\CHAP14\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP15
VERILOG_BOOK_EXAMPLES\CHAP15\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP2
VERILOG_BOOK_EXAMPLES\CHAP2\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP2\CHAP_EG\ILLEGAL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP2\CHAP_EG\ILLEGAL.V
VERILOG_BOOK_EXAMPLES\CHAP2\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP2\CHAP_EG\RIPPLE.SPJ
VERILOG_BOOK_EXAMPLES\CHAP2\CHAP_EG\RIPPLE.V
VERILOG_BOOK_EXAMPLES\CHAP2\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP2\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP2\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP3
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\DISPLAY.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\DISPLAY.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\INTEGER.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\INTEGER.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\MONITOR.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\MONITOR.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\REAL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\REAL.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\REG.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\REG.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\STOP_FIN.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\STOP_FIN.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\STRING.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\STRING.V
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\TIME.SPJ
VERILOG_BOOK_EXAMPLES\CHAP3\CHAP_EG\TIME.V
VERILOG_BOOK_EXAMPLES\CHAP3\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP3\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP3\EXERCISE\EX2.V
VERILOG_BOOK_EXAMPLES\CHAP3\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP4
VERILOG_BOOK_EXAMPLES\CHAP4\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP4\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP4\CHAP_EG\SR_LATCH.SPJ
VERILOG_BOOK_EXAMPLES\CHAP4\CHAP_EG\SR_LATCH.V
VERILOG_BOOK_EXAMPLES\CHAP4\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP4\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP4\EXERCISE\EX3.SPJ
VERILOG_BOOK_EXAMPLES\CHAP4\EXERCISE\EX3.V
VERILOG_BOOK_EXAMPLES\CHAP4\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP5
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\DELAY.SPJ
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\DELAY.V
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\FULLADD.SPJ
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\FULLADD.V
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\MUX4_1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\MUX4_1.V
VERILOG_BOOK_EXAMPLES\CHAP5\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP5\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP5\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP5\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP5\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP6
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\COUNTER.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\COUNTER.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\FULADD1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\FULLADD1.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\FULLADD2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\FULLADD2.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\IMP_DEL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\IMP_DEL.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\MUX_1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\MUX_1.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\MUX_2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\MUX_2.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\NET_DECL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\NET_DECL.V
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\REG_DECL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\CHAP_EG\REG_DEL.V
VERILOG_BOOK_EXAMPLES\CHAP6\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP6\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP6\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP6\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP7
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\ALWAYS.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\ALWAYS.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\BLOCK.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\BLOCK.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\COUNTER.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\COUNTER.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\DEMUX1_4.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\DEMUX1_4.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\DISABLE.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\DISABLE.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\EVENT_OR.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\EVENT_OR.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\FOR.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\FOR.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\FOREVER1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\FOREVER1.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\FOREVER2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\FOREVER2.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\INITIAL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\INITIAL.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\MUX4_1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\MUX4_1.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\NESTED.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\NESTED.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\NONBLOCK.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\NONBLOCK.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\PARALLEL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\PARALLEL.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\REG_DEL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\REG_DEL.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\REPEAT1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\REPEAT1.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\REPEAT2.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\SEQ.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\SEQ.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\SIG_CTRL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\SIG_CTRL.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\WHILE1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\WHILE1.V
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\WHILE2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\CHAP_EG\WHILE2.V
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX2.V
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX3.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX3.V
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX4.SPJ
VERILOG_BOOK_EXAMPLES\CHAP7\EXERCISE\EX4.V
VERILOG_BOOK_EXAMPLES\CHAP7\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP8
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\FUNC1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\FUNC1.V
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\FUNC2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\FUNC2.V
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\TASK1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\TASK1.V
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\TASK2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP8\CHAP_EG\TASK2.V
VERILOG_BOOK_EXAMPLES\CHAP8\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP8\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP8\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP8\EXERCISE\EX4.SPJ
VERILOG_BOOK_EXAMPLES\CHAP8\EXERCISE\EX4.V
VERILOG_BOOK_EXAMPLES\CHAP8\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP9
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\CON_COMP.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\CON_COMP.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\CON_EXEC.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\CON_EXEC.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\EDGE_DFF.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\FILES.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\FILES.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\FOR-REL.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\HIER.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\HIER.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\INIT.DAT
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\MEMORY.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\MEMORY.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\PARAM1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\PARAM1.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\PARAM2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\PARAM2.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\PARAM3.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\PARAM3.V
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\README.TXT
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\TIMESCL.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\CHAP_EG\TIMESCL.V
VERILOG_BOOK_EXAMPLES\CHAP9\EXERCISE
VERILOG_BOOK_EXAMPLES\CHAP9\EXERCISE\EX1.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\EXERCISE\EX1.V
VERILOG_BOOK_EXAMPLES\CHAP9\EXERCISE\EX2.SPJ
VERILOG_BOOK_EXAMPLES\CHAP9\EXERCISE\EX2.V
VERILOG_BOOK_EXAMPLES\CHAP9\README.TXT
VERILOG_BOOK_EXAMPLES\README.TXT
(Prentice) Verilog HDL--Guide to Digital Design & Synthesis (2nd[1].Ed.).chm