文件名称:an_dcfifo_top_restored
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alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ，值得学习。
实现高速到低速时钟域的数据传输 ，值得学习。
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压缩包 : 13898393an_dcfifo_top_restored.rar 列表 an_dcfifo_top_restored\an473.pdf an_dcfifo_top_restored\an_dcfifo_top.qarlog an_dcfifo_top_restored\an_dcfifo_top.qpf an_dcfifo_top_restored\an_dcfifo_top.qsf an_dcfifo_top_restored\an_dcfifo_top.qws an_dcfifo_top_restored\an_dcfifo_top.v an_dcfifo_top_restored\an_dcfifo_top_assignment_defaults.qdf an_dcfifo_top_restored\an_dcfifo_top_fast_to_slow.sdc an_dcfifo_top_restored\an_dcfifo_top_fast_to_slow.vwf an_dcfifo_top_restored\an_dcfifo_top_slow_to_fast.sdc an_dcfifo_top_restored\an_dcfifo_top_slow_to_fast.vwf an_dcfifo_top_restored\assignment_defaults.qdf an_dcfifo_top_restored\db\an_dcfifo_top.db_info an_dcfifo_top_restored\db\an_dcfifo_top.eco.cdb an_dcfifo_top_restored\db\an_dcfifo_top.sld_design_entry.sci an_dcfifo_top_restored\db an_dcfifo_top_restored\dcfifo8X32.v an_dcfifo_top_restored\myrom.hex an_dcfifo_top_restored\ram256X32.v an_dcfifo_top_restored\ram256X32_bb.v an_dcfifo_top_restored\read_control_logic.v an_dcfifo_top_restored\rom256X32.v an_dcfifo_top_restored\simulation\modelsim\an_dcfifo_top.vo an_dcfifo_top_restored\simulation\modelsim\an_dcfifo_top_fast_to_slow.vt an_dcfifo_top_restored\simulation\modelsim\an_dcfifo_top_slow_to_fast.vt an_dcfifo_top_restored\simulation\modelsim\an_dcfifo_top_v.sdo an_dcfifo_top_restored\simulation\modelsim\fast_to_slow_gate.do an_dcfifo_top_restored\simulation\modelsim\fast_to_slow_rtl.do an_dcfifo_top_restored\simulation\modelsim\gate_wave.do an_dcfifo_top_restored\simulation\modelsim\modelsim.ini an_dcfifo_top_restored\simulation\modelsim\myrom.hex an_dcfifo_top_restored\simulation\modelsim\rtl_wave.do an_dcfifo_top_restored\simulation\modelsim\slow_to_fast_gate.do an_dcfifo_top_restored\simulation\modelsim\slow_to_fast_rtl.do an_dcfifo_top_restored\simulation\modelsim an_dcfifo_top_restored\simulation an_dcfifo_top_restored\write_control_logic.v an_dcfifo_top_restored