文件名称:4bit_buma_adder
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing, adder module ahead of the last bit adder, including test bed, through the Modelsim, Synplify simulation.
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下载文件列表
4bit_buma_adder
...............\adder.v
...............\adderfms.v
...............\add_top.v
...............\adder.v
...............\adderfms.v
...............\add_top.v