文件名称:VHDLexample

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Text]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 322kb
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  • 0次
  • 提 供 者:
  • 森*
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vhdl 语言实例,包括各种逻辑门的构造。-Examples of VHDL language, including a variety of logic gate structure.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VHDL语言100

...........\100vhdl例子

...........\...........\10_function

...........\...........\...........\10_bit_to_int.vhd

...........\...........\...........\README.TXT

...........\...........\11_wiredor

...........\...........\..........\11_wiredor.vhd

...........\...........\..........\README.TXT

...........\...........\12_convert

...........\...........\..........\12_convert.vhd

...........\...........\..........\README.TXT

...........\...........\13_SHL

...........\...........\......\13_SHL.VHD

...........\...........\......\README.TXT

...........\...........\14_MVL7_functions

...........\...........\.................\14_MVL7_functions.vhd

...........\...........\.................\README.TXT

...........\...........\15_MUX41

...........\...........\........\15_MUX41.VHD

...........\...........\........\15_MVL7_functions.vhd

...........\...........\........\15_MVL7_syn_types.vhd

...........\...........\........\15_test_vectors_mux41.vhd

...........\...........\........\15_TYPES.VHD

...........\...........\........\README.TXT

...........\...........\16_MUX

...........\...........\......\16_multiple_mux.vhd

...........\...........\......\16_MVL7_functions.vhd

...........\...........\......\16_test_vectors.vhd

...........\...........\......\16_TYPES.VHD

...........\...........\......\README.TXT

...........\...........\......\TYPES.VHD

...........\...........\17_parity

...........\...........\.........\17_parity.vhd

...........\...........\.........\17_test_bench.vhd

...........\...........\.........\README.TXT

...........\...........\18_LIB

...........\...........\......\18_tech_lib.vhd

...........\...........\......\18_test_lib.vhd

...........\...........\......\README.TXT

...........\...........\19_test_194

...........\...........\...........\19_test_194.vhd

...........\...........\1_ADDER

...........\...........\.......\1_ADDER

...........\...........\.......\.......\1_ADDER.exp

...........\...........\.......\.......\files

...........\...........\.......\.......\.....\L1.rpt

...........\...........\.......\.......\.....\L2.rpt

...........\...........\.......\.......\.....\L3.rpt

...........\...........\.......\.......\workdirs

...........\...........\.......\.......\........\aa

...........\...........\.......\.......\........\..\ADDER.sim

...........\...........\.......\.......\........\..\ADDER.syn

...........\...........\.......\.......\........\..\Anal.info

...........\...........\.......\.......\........\..\Anal.out

...........\...........\.......\.......\........\WORK

...........\...........\.......\.......\........\....\Anal.info

...........\...........\.......\.......\........\....\Anal.out

...........\...........\.......\.......\........\....\BIT_RTL_ADDER.sim

...........\...........\.......\.......\........\....\BIT_RTL_ADDER.syn

...........\...........\.......\1_adder.acf

...........\...........\.......\1_adder.hif

...........\...........\.......\1_adder.mmf

...........\...........\.......\1_ADDER.VHD

...........\...........\.......\bir_rtl_adder.acf

...........\...........\.......\bir_rtl_adder.hif

...........\...........\.......\bir_rtl_adder.mmf

...........\...........\.......\bir_rtl_adder.tdf

...........\...........\.......\bit_rtl_adder.acf

...........\...........\.......\bit_rtl_adder.hif

...........\...........\.......\bit_rtl_adder.mmf

...........\...........\.......\bit_rtl_adder.vhd

...........\...........\.......\LIB.DLS

...........\...........\.......\README.TXT

...........\...........\.......\U2268397.DLS

...........\...........\20_test_159

...........\...........\...........\20_test_159.vhd

...........\...........\21_test_13a

...........\...........\...........\21_test_13a.vhd

...........\...........\22_deadlock

...........\...........\...........\22_deadlock.vhd

...........\...........\23_test_120

...........\...........\...........\23_Test_120.vhd

...........\...........\24_test_195

...........\...........\...........\24_test_195.vhd

...........\...........\25_test_1

...........\...........\.........\25_test_1.vhd

...........\...........\.........\25_test_1a.vhd

...........\...........\2

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