文件名称:PWM
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脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
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Pulse-width
modulation
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vhdl
coding
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下载文件列表
脉冲宽度调制
............\an501.pdf
............\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example
............\.............................................................\code
............\.............................................................\....\pwm_main.v
............\.............................................................\modelsim
............\.............................................................\........\pulse_width_modulator.cr.mti
............\.............................................................\........\pulse_width_modulator.mpf
............\.............................................................\........\pwm_main.v
............\.............................................................\........\pwm_sim.cr.mti
............\.............................................................\........\pwm_sim.mpf
............\.............................................................\........\test_pwm.v
............\.............................................................\........\wave.do
............\.............................................................\........\wave2.do
............\.............................................................\........\wave3.do
............\.............................................................\........\wave4.do
............\.............................................................\........\wave5.do
............\.............................................................\........\work
............\.............................................................\........\....\altufm_osc0_altufm_osc_1p3
............\.............................................................\........\....\..........................\verilog.asm
............\.............................................................\........\....\..........................\_primary.dat
............\.............................................................\........\....\..........................\_primary.vhd
............\.............................................................\........\....\clkgen
............\.............................................................\........\....\......\verilog.asm
............\.............................................................\........\....\......\_primary.dat
............\.............................................................\........\....\......\_primary.vhd
............\.............................................................\........\....\clk_gen
............\.............................................................\........\....\.......\verilog.asm
............\.............................................................\........\....\.......\_primary.dat
............\.............................................................\........\....\.......\_primary.vhd
............\.............................................................\........\....\dutycycle
............\.............................................................\........\....\.........\verilog.asm
............\.............................................................\........\....\.........\_primary.dat
............\.............................................................\........\....\.........\_primary.vhd
............\.............................................................\........\....\duty_cycle
............\.............................................................\........\....\..........\verilog.asm
............\.............................................................\........\....\..........\_primary.dat
............\.............................................................\........\....\..........\_primary.vhd
............\.............................................................\........\....\pwm_gen
............\.............................................................\........\....\.......\verilog.asm
............\.............................................................\........\....\.......\_primary.dat
............\.............
............\an501.pdf
............\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example
............\.............................................................\code
............\.............................................................\....\pwm_main.v
............\.............................................................\modelsim
............\.............................................................\........\pulse_width_modulator.cr.mti
............\.............................................................\........\pulse_width_modulator.mpf
............\.............................................................\........\pwm_main.v
............\.............................................................\........\pwm_sim.cr.mti
............\.............................................................\........\pwm_sim.mpf
............\.............................................................\........\test_pwm.v
............\.............................................................\........\wave.do
............\.............................................................\........\wave2.do
............\.............................................................\........\wave3.do
............\.............................................................\........\wave4.do
............\.............................................................\........\wave5.do
............\.............................................................\........\work
............\.............................................................\........\....\altufm_osc0_altufm_osc_1p3
............\.............................................................\........\....\..........................\verilog.asm
............\.............................................................\........\....\..........................\_primary.dat
............\.............................................................\........\....\..........................\_primary.vhd
............\.............................................................\........\....\clkgen
............\.............................................................\........\....\......\verilog.asm
............\.............................................................\........\....\......\_primary.dat
............\.............................................................\........\....\......\_primary.vhd
............\.............................................................\........\....\clk_gen
............\.............................................................\........\....\.......\verilog.asm
............\.............................................................\........\....\.......\_primary.dat
............\.............................................................\........\....\.......\_primary.vhd
............\.............................................................\........\....\dutycycle
............\.............................................................\........\....\.........\verilog.asm
............\.............................................................\........\....\.........\_primary.dat
............\.............................................................\........\....\.........\_primary.vhd
............\.............................................................\........\....\duty_cycle
............\.............................................................\........\....\..........\verilog.asm
............\.............................................................\........\....\..........\_primary.dat
............\.............................................................\........\....\..........\_primary.vhd
............\.............................................................\........\....\pwm_gen
............\.............................................................\........\....\.......\verilog.asm
............\.............................................................\........\....\.......\_primary.dat
............\.............