文件名称:match_rec
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使用VERILOG实现QPSK信号的匹配滤波，对符号过采样率为4，在程序中设定相关峰的检测门限为3-脢 鹿 脫脙VERILOG脢渭脧脰QPSK脨脜 潞 脜渭脛脝 楼 脜盲脗脣 虏篓拢卢露 脭 没 潞 脜 鹿 媒 虏 脡脩霉脗脢脦 陋 4 拢 卢 脭脷 鲁 脤脨貌脰脨脡猫 露 篓 脧脿 鹿 脴 氓渭脛 录 矛 虏 芒脙脜脧脼脦 陋 3
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下载文件列表
match_rec
.........\AutoConstraint_match_rec.sdc
.........\backup
.........\match_rec.edn
.........\match_rec.fse
.........\match_rec.htm
.........\match_rec.ise
.........\match_rec.map
.........\match_rec.ncf
.........\match_rec.prj
.........\match_rec.restore
.........\match_rec.sap
.........\match_rec.sdc
.........\match_rec.srd
.........\match_rec.srm
.........\match_rec.srr
.........\match_rec.srs
.........\match_rec.szr
.........\match_rec.tlg
.........\match_rec.v
.........\match_rec_compile.tcl
.........\match_rec_map.tcl
.........\match_rec_summary.html
.........\match_rec_xdb
.........\.............\tmp
.........\rpt_match_rec.areasrr
.........\rpt_match_rec_areasrr.htm
.........\run_options.txt
.........\stdout.log
.........\syntmp
.........\......\match_rec.msg
.........\......\match_rec.plg
.........\......\match_rec_flink.htm
.........\......\match_rec_srr.htm
.........\......\match_rec_toc.htm
.........\......\sap.log
.........\test_match_rec.fdo
.........\test_match_rec.udo
.........\test_match_rec.v
.........\test_match_rec_wave.fdo
.........\transcript
.........\verif
.........\.....\match_rec.vif
.........\vsim.wlf
.........\work
.........\....\glbl
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\match_rec
.........\....\.........\_primary.dat
.........\....\.........\_primary.vhd
.........\....\test_match_rec
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\_info
.........\....\_opt
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_secureip__info
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_unimacro_ver__info
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_unisims_ver__info
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_XilinxCoreLib_ver__info
.........\....\....\work_glbl_fast.asm
.........\....\....\work_glbl_fast.dt2
.........\....\....\work_match_rec_fast.asm
.........\....\....\work_match_rec_fast.dt2
.........\....\....\work_test_match_rec_fast.asm
.........\....\....\work_test_match_rec_fast.dt2
.........\....\....\work__info
.........\....\....\_deps
.........\....\_temp
.........\_xmsgs
.........\AutoConstraint_match_rec.sdc
.........\backup
.........\match_rec.edn
.........\match_rec.fse
.........\match_rec.htm
.........\match_rec.ise
.........\match_rec.map
.........\match_rec.ncf
.........\match_rec.prj
.........\match_rec.restore
.........\match_rec.sap
.........\match_rec.sdc
.........\match_rec.srd
.........\match_rec.srm
.........\match_rec.srr
.........\match_rec.srs
.........\match_rec.szr
.........\match_rec.tlg
.........\match_rec.v
.........\match_rec_compile.tcl
.........\match_rec_map.tcl
.........\match_rec_summary.html
.........\match_rec_xdb
.........\.............\tmp
.........\rpt_match_rec.areasrr
.........\rpt_match_rec_areasrr.htm
.........\run_options.txt
.........\stdout.log
.........\syntmp
.........\......\match_rec.msg
.........\......\match_rec.plg
.........\......\match_rec_flink.htm
.........\......\match_rec_srr.htm
.........\......\match_rec_toc.htm
.........\......\sap.log
.........\test_match_rec.fdo
.........\test_match_rec.udo
.........\test_match_rec.v
.........\test_match_rec_wave.fdo
.........\transcript
.........\verif
.........\.....\match_rec.vif
.........\vsim.wlf
.........\work
.........\....\glbl
.........\....\....\_primary.dat
.........\....\....\_primary.vhd
.........\....\match_rec
.........\....\.........\_primary.dat
.........\....\.........\_primary.vhd
.........\....\test_match_rec
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\_info
.........\....\_opt
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_secureip__info
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_unimacro_ver__info
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_unisims_ver__info
.........\....\....\D__Program_FPGA_software_ModelSim_xilinx_lib_XilinxCoreLib_ver__info
.........\....\....\work_glbl_fast.asm
.........\....\....\work_glbl_fast.dt2
.........\....\....\work_match_rec_fast.asm
.........\....\....\work_match_rec_fast.dt2
.........\....\....\work_test_match_rec_fast.asm
.........\....\....\work_test_match_rec_fast.dt2
.........\....\....\work__info
.........\....\....\_deps
.........\....\_temp
.........\_xmsgs