文件名称:clock
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数字秒表的设计，reset为归零设置，start为重新计时设置-Design of digital stopwatch, reset to zero settings, start time set for the re-
相关搜索： stopwatch
digital
vhdl
clock
vhdl
CLOCK
秒表
digital
clock
vhdl
StopWatch
绉掕〃
DIGITAL
CLOCK
秒表
设计
stopwatch
vhdl
digital
vhdl
clock
vhdl
CLOCK
秒表
digital
clock
vhdl
StopWatch
绉掕〃
DIGITAL
CLOCK
秒表
设计
stopwatch
vhdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
数字秒表的设计
..............\clkgen.bsf
..............\clkgen.vhd
..............\cmp_state.ini
..............\cnt.bsf
..............\cnt.vhd
..............\db
..............\..\time.asm.qmsg
..............\..\time.cbx.xml
..............\..\time.cmp.cdb
..............\..\time.cmp.hdb
..............\..\time.cmp.rdb
..............\..\time.cmp.tdb
..............\..\time.cmp0.ddb
..............\..\time.db_info
..............\..\time.eco.cdb
..............\..\time.fit.qmsg
..............\..\time.hier_info
..............\..\time.hif
..............\..\time.map.cdb
..............\..\time.map.hdb
..............\..\time.map.qmsg
..............\..\time.pre_map.cdb
..............\..\time.pre_map.hdb
..............\..\time.psp
..............\..\time.rtlv.hdb
..............\..\time.rtlv_sg.cdb
..............\..\time.rtlv_sg_swap.cdb
..............\..\time.sgdiff.cdb
..............\..\time.sgdiff.hdb
..............\..\time.signalprobe.cdb
..............\..\time.sld_design_entry.sci
..............\..\time.sld_design_entry_dsc.sci
..............\..\time.syn_hier_info
..............\..\time.tan.qmsg
..............\..\time_cmp.qrpt
..............\decoder.bsf
..............\decoder.vhd
..............\time.asm.rpt
..............\time.bdf
..............\time.cdf
..............\time.done
..............\time.fit.eqn
..............\time.fit.rpt
..............\time.fit.summary
..............\time.flow.rpt
..............\time.map.eqn
..............\time.map.rpt
..............\time.map.summary
..............\time.pin
..............\time.pof
..............\time.qpf
..............\time.qsf
..............\time.qws
..............\time.sof
..............\time.tan.rpt
..............\time.tan.summary
..............\xianshi.bsf
..............\xianshi.vhd
..............\clkgen.bsf
..............\clkgen.vhd
..............\cmp_state.ini
..............\cnt.bsf
..............\cnt.vhd
..............\db
..............\..\time.asm.qmsg
..............\..\time.cbx.xml
..............\..\time.cmp.cdb
..............\..\time.cmp.hdb
..............\..\time.cmp.rdb
..............\..\time.cmp.tdb
..............\..\time.cmp0.ddb
..............\..\time.db_info
..............\..\time.eco.cdb
..............\..\time.fit.qmsg
..............\..\time.hier_info
..............\..\time.hif
..............\..\time.map.cdb
..............\..\time.map.hdb
..............\..\time.map.qmsg
..............\..\time.pre_map.cdb
..............\..\time.pre_map.hdb
..............\..\time.psp
..............\..\time.rtlv.hdb
..............\..\time.rtlv_sg.cdb
..............\..\time.rtlv_sg_swap.cdb
..............\..\time.sgdiff.cdb
..............\..\time.sgdiff.hdb
..............\..\time.signalprobe.cdb
..............\..\time.sld_design_entry.sci
..............\..\time.sld_design_entry_dsc.sci
..............\..\time.syn_hier_info
..............\..\time.tan.qmsg
..............\..\time_cmp.qrpt
..............\decoder.bsf
..............\decoder.vhd
..............\time.asm.rpt
..............\time.bdf
..............\time.cdf
..............\time.done
..............\time.fit.eqn
..............\time.fit.rpt
..............\time.fit.summary
..............\time.flow.rpt
..............\time.map.eqn
..............\time.map.rpt
..............\time.map.summary
..............\time.pin
..............\time.pof
..............\time.qpf
..............\time.qsf
..............\time.qws
..............\time.sof
..............\time.tan.rpt
..............\time.tan.summary
..............\xianshi.bsf
..............\xianshi.vhd