文件名称:ALTERA_DE2_FSM_VHDL
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This an exercise in using finite state machines.基于ALTERA的DE2开发
平台，设计一个有限状态机FSM(finite state machines).-This an exercise in using finite state machines. Based on ALTERA s DE2 development platform to design a finite state machine FSM (finite state machines).
平台，设计一个有限状态机FSM(finite state machines).-This an exercise in using finite state machines. Based on ALTERA s DE2 development platform to design a finite state machine FSM (finite state machines).
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lab7_VHDL.pdf