文件名称:8b_10b
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vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
Asynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
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(系统自动生成,下载前可以参看下载内容)
下载文件列表
8b_10b
......\8b10b_encdec_v1d0[1].pdf
......\8b10_dec.vhd
......\8b10_enc.vhd
......\encdec_8b10b_TB.vhd
......\enc_8b10b_TB.vhd
......\8b10b_encdec_v1d0[1].pdf
......\8b10_dec.vhd
......\8b10_enc.vhd
......\encdec_8b10b_TB.vhd
......\enc_8b10b_TB.vhd