文件名称:dmf_pn_catch
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采用匹配滤波，实现伪码捕获功能，模块内部可以产生简单噪声来验证捕获性能(verilog)-Matched filter used to achieve pseudo-code capture functionality, the module can generate simple internal noise to verify the performance capture (verilog)
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下载文件列表
dmf_pn_catch
............\automake.log
............\BPSK.dhp
............\BPSK.ise
............\BPSK.ise_ISE_Backup
............\bpsk34
............\bpsk34.wlf
............\core.tpl
............\dcm165m.xaw
............\dcm165m_arwz.ucf
............\decode_bpsk_34_vhdl.prj
............\div3.asy
............\div3.sym
............\div3.veo
............\div3.xco
............\encode34_s.vhd
............\encode_bpsk_vhdl.prj
............\fbusif.vhd
............\fifo_code.vhd
............\fpgab_top.v
............\fpgab_ucf.cel
............\fpgab_ucf.ucf
............\gen_clk.v
............\max_min_vhdl.prj
............\noise_gen_one_bit.v
............\p2.jhd
............\p2.tbw
............\p2.udo
............\p2.xwv
............\pn_catch.v
............\pn_catch_83_test.v
............\pn_catch_vhdl.prj
............\pn_code_1023.v
............\pn_test.jhd
............\pn_test.tbw
............\pn_test.udo
............\pn_test.xwv
............\pn_test.xwv_bak
............\transcript
............\vish_stacktrace.vstf
............\viterbi.vhd
............\viterbi12_s.vhd
............\work
............\....\bit_stat
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\bus_operation_@f@p@g@a@b
............\....\........................\verilog.asm
............\....\........................\_primary.dat
............\....\........................\_primary.vhd
............\....\clk_en_numb
............\....\...........\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\clk_loop_4
............\....\..........\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\data_reg
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\data_source
............\....\...........\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\dcm165m
............\....\.......\behavioral.asm
............\....\.......\behavioral.dat
............\....\.......\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\decode_@b@p@s@k_12
............\....\..................\verilog.asm
............\....\..................\_primary.dat
............\....\..................\_primary.vhd
............\....\decode_@b@p@s@k_34
............\....\..................\verilog.asm
............\....\..................\_primary.dat
............\....\..................\_primary.vhd
............\....\dec_syn
............\....\.......\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\div3
............\....\....\div3_a.asm
............\....\....\div3_a.dat
............\....\....\_primary.dat
............\....\encode12
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\encode12test
............\....\............\verilog.asm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\encode12_s
............\....\..........\encode12_s_a.asm
............\....\..........\encode12_s_a.dat
............\automake.log
............\BPSK.dhp
............\BPSK.ise
............\BPSK.ise_ISE_Backup
............\bpsk34
............\bpsk34.wlf
............\core.tpl
............\dcm165m.xaw
............\dcm165m_arwz.ucf
............\decode_bpsk_34_vhdl.prj
............\div3.asy
............\div3.sym
............\div3.veo
............\div3.xco
............\encode34_s.vhd
............\encode_bpsk_vhdl.prj
............\fbusif.vhd
............\fifo_code.vhd
............\fpgab_top.v
............\fpgab_ucf.cel
............\fpgab_ucf.ucf
............\gen_clk.v
............\max_min_vhdl.prj
............\noise_gen_one_bit.v
............\p2.jhd
............\p2.tbw
............\p2.udo
............\p2.xwv
............\pn_catch.v
............\pn_catch_83_test.v
............\pn_catch_vhdl.prj
............\pn_code_1023.v
............\pn_test.jhd
............\pn_test.tbw
............\pn_test.udo
............\pn_test.xwv
............\pn_test.xwv_bak
............\transcript
............\vish_stacktrace.vstf
............\viterbi.vhd
............\viterbi12_s.vhd
............\work
............\....\bit_stat
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\bus_operation_@f@p@g@a@b
............\....\........................\verilog.asm
............\....\........................\_primary.dat
............\....\........................\_primary.vhd
............\....\clk_en_numb
............\....\...........\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\clk_loop_4
............\....\..........\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\data_reg
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\data_source
............\....\...........\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\dcm165m
............\....\.......\behavioral.asm
............\....\.......\behavioral.dat
............\....\.......\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\decode_@b@p@s@k_12
............\....\..................\verilog.asm
............\....\..................\_primary.dat
............\....\..................\_primary.vhd
............\....\decode_@b@p@s@k_34
............\....\..................\verilog.asm
............\....\..................\_primary.dat
............\....\..................\_primary.vhd
............\....\dec_syn
............\....\.......\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\div3
............\....\....\div3_a.asm
............\....\....\div3_a.dat
............\....\....\_primary.dat
............\....\encode12
............\....\........\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\encode12test
............\....\............\verilog.asm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\encode12_s
............\....\..........\encode12_s_a.asm
............\....\..........\encode12_s_a.dat