文件名称:ethernet__verilog
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fpga模拟以太网物理层的源代码，用verilog硬件描述语言开发。-FPGA simulation of the Ethernet physical layer of the source code, using Verilog hardware descr iption language development.
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ethernet__verilog
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.................\...\.......\eth_maccontrol.v
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.................\...\.......\eth_receivecontrol.v
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.................\...\.......\eth_rxcounters.v
.................\...\.......\eth_rxethmac.v
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.................\...\.......\eth_sync_clk1_clk2.v
.................\...\.......\eth_top.v
.................\...\.......\eth_transmitcontrol.v
.................\...\.......\eth_txcounters.v
.................\...\.......\eth_txethmac.v
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.................\...\.......\eth_clockgen.v
.................\...\.......\eth_crc.v
.................\...\.......\eth_defines.v
.................\...\.......\eth_maccontrol.v
.................\...\.......\eth_macstatus.v
.................\...\.......\eth_miim.v
.................\...\.......\eth_outputcontrol.v
.................\...\.......\eth_random.v
.................\...\.......\eth_receivecontrol.v
.................\...\.......\eth_register.v
.................\...\.......\eth_registers.v
.................\...\.......\eth_rxcounters.v
.................\...\.......\eth_rxethmac.v
.................\...\.......\eth_rxstatem.v
.................\...\.......\eth_shiftreg.v
.................\...\.......\eth_sync_clk1_clk2.v
.................\...\.......\eth_top.v
.................\...\.......\eth_transmitcontrol.v
.................\...\.......\eth_txcounters.v
.................\...\.......\eth_txethmac.v
.................\...\.......\eth_txstatem.v
.................\...\.......\eth_wishbonedma.v
.................\...\.......\timescale.v
.................\sim
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