文件名称:AD_DA

  • 所属分类:
  • matlab例程
  • 资源属性:
  • [Matlab] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 535kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 杨**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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使用MATLAB工具,对信号进行采集调制,再进行信号解码.对信号进行算法控制.-The use of MATLAB tools, modulation of signal acquisition, and then decode the signal. The signal control algorithm.
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下载文件列表

AD_DA

.....\adctest.mdl

.....\dac_test.err

.....\dac_test.mdl

.....\dac_test_black_box1_wrapper.v

.....\dac_test_black_box_wrapper.v

.....\fir_160_tap.v

.....\fir_top.fsdb

.....\fir_top.v

.....\fir_top_config.m

.....\fm_test.mdl

.....\iir_6_filter.v

.....\iir_filter.v

.....\iir_filter_config.m

.....\isimwavedata.xwv

.....\rom.txt

.....\sig_test.mdl

.....\sysgenADCDAC.mdl

.....\sysgenADCDAC_PreLoadFcn.m

.....\test.fsdb

.....\transcript

.....\untitled.fda

.....\work

.....\....\asr_ram

.....\....\.......\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\dac_test_black_box1_wrapper

.....\....\...........................\verilog.asm

.....\....\...........................\_primary.dat

.....\....\...........................\_primary.vhd

.....\....\dac_test_black_box_wrapper

.....\....\..........................\verilog.asm

.....\....\..........................\_primary.dat

.....\....\..........................\_primary.vhd

.....\....\fir_160_tap

.....\....\...........\verilog.asm

.....\....\...........\_primary.dat

.....\....\...........\_primary.vhd

.....\....\fir_asr

.....\....\.......\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\fir_mac

.....\....\.......\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\fir_rom

.....\....\.......\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\fir_top

.....\....\.......\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\iir_6_filter

.....\....\............\verilog.asm

.....\....\............\_primary.dat

.....\....\............\_primary.vhd

.....\....\iir_filter

.....\....\..........\verilog.asm

.....\....\..........\_primary.dat

.....\....\..........\_primary.vhd

.....\....\xlcosim_dac_test_modelsim

.....\....\.........................\structural.asm

.....\....\.........................\structural.dat

.....\....\.........................\_primary.dat

.....\....\xlcosim_dac_test_modelsim_clk_drvr

.....\....\..................................\behavior.asm

.....\....\..................................\behavior.dat

.....\....\..................................\_primary.dat

.....\....\xlcosim_fli_controller

.....\....\......................\only.asm

.....\....\......................\only.dat

.....\....\......................\_primary.dat

.....\....\_info

.....\xlcosim_dac_test_modelsim.tcl

.....\xlcosim_dac_test_modelsim.vhd

.....\xlcosim_dac_test_modelsimf.vhd

.....\xlcosim_dac_test_modelsim_clk_drvr.vhd

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