文件名称:chap9
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《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6
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chap9
.....\bidir.v
.....\bidir2.v
.....\code_83.v
.....\decode47.v
.....\decoder_38.v
.....\dff.v
.....\dff1.v
.....\dff2.v
.....\encoder8_3.v
.....\gate1.v
.....\gate2.v
.....\gate3.v
.....\jk_ff.v
.....\johnson.v
.....\latch_1.v
.....\latch_2.v
.....\latch_8.v
.....\mac.v
.....\mac_tp.v
.....\map_lpm_ram.v
.....\mpc.v
.....\mpc_tp.v
.....\mux_case.v
.....\mux_if.v
.....\parity.v
.....\ram256x8.v
.....\reg8.v
.....\rom.v
.....\serial_pal.v
.....\shifter.v
.....\tri_1.v
.....\tri_2.v
.....\updown_count.v
.....\bidir.v
.....\bidir2.v
.....\code_83.v
.....\decode47.v
.....\decoder_38.v
.....\dff.v
.....\dff1.v
.....\dff2.v
.....\encoder8_3.v
.....\gate1.v
.....\gate2.v
.....\gate3.v
.....\jk_ff.v
.....\johnson.v
.....\latch_1.v
.....\latch_2.v
.....\latch_8.v
.....\mac.v
.....\mac_tp.v
.....\map_lpm_ram.v
.....\mpc.v
.....\mpc_tp.v
.....\mux_case.v
.....\mux_if.v
.....\parity.v
.....\ram256x8.v
.....\reg8.v
.....\rom.v
.....\serial_pal.v
.....\shifter.v
.....\tri_1.v
.....\tri_2.v
.....\updown_count.v