文件名称:chap7
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《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4
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chap7
.....\add4_1.v
.....\add4_2.v
.....\add4_3.v
.....\count4.v
.....\full_add1.v
.....\full_add2.v
.....\full_add3.v
.....\full_add4.v
.....\full_add5.v
.....\half_add1.v
.....\half_add2.v
.....\half_add3.v
.....\half_add4.v
.....\mux2_1a.v
.....\mux2_1b.v
.....\mux2_1c.v
.....\mux4_1a.v
.....\mux4_1b.v
.....\mux4_1c.v
.....\mux4_1d.v
.....\add4_1.v
.....\add4_2.v
.....\add4_3.v
.....\count4.v
.....\full_add1.v
.....\full_add2.v
.....\full_add3.v
.....\full_add4.v
.....\full_add5.v
.....\half_add1.v
.....\half_add2.v
.....\half_add3.v
.....\half_add4.v
.....\mux2_1a.v
.....\mux2_1b.v
.....\mux2_1c.v
.....\mux4_1a.v
.....\mux4_1b.v
.....\mux4_1c.v
.....\mux4_1d.v