文件名称:lookup_multi
- 所属分类：
- 图形图像处理(光照,映射..)
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1kb
- 下载次数：
- 0次
- 提 供 者：
- stev*****
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- 无
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//4×4 查找表乘法器
module mult4x4(out,a,b,clk)
output[7:0] out
input[3:0] a,b
input clk
reg[7:0] out
reg[1:0] firsta,firstb
reg[1:0] seconda,secondb
wire[3:0] outa,outb,outc,outd
always @(posedge clk)
begin
firsta = a[3:2] seconda = a[1:0]
firstb = b[3:2] secondb = b[1:0]
end
lookup m1(outa,firsta,firstb,clk),
m2(outb,firsta,secondb,clk),
m3(outc,seconda,firstb,clk),
m4(outd,seconda,secondb,clk) //模块调用-//4 × 4 multiplier lookup table module mult4x4 (out, a, b, clk) output [7:0] out input [3:0] a, b input clk reg [7:0] out reg [1:0 ] firsta, firstb reg [1:0] seconda, secondb wire [3:0] outa, outb, outc, outd always @ (posedge clk) beginfirsta = a [3:2] seconda = a [1:0] firstb = b [3:2] secondb = b [1:0] endlookup m1 (outa, firsta, firstb, clk), m2 (outb, firsta, secondb, clk), m3 (outc, seconda, firstb, clk), m4 ( outd, seconda, secondb, clk)// module call
module mult4x4(out,a,b,clk)
output[7:0] out
input[3:0] a,b
input clk
reg[7:0] out
reg[1:0] firsta,firstb
reg[1:0] seconda,secondb
wire[3:0] outa,outb,outc,outd
always @(posedge clk)
begin
firsta = a[3:2] seconda = a[1:0]
firstb = b[3:2] secondb = b[1:0]
end
lookup m1(outa,firsta,firstb,clk),
m2(outb,firsta,secondb,clk),
m3(outc,seconda,firstb,clk),
m4(outd,seconda,secondb,clk) //模块调用-//4 × 4 multiplier lookup table module mult4x4 (out, a, b, clk) output [7:0] out input [3:0] a, b input clk reg [7:0] out reg [1:0 ] firsta, firstb reg [1:0] seconda, secondb wire [3:0] outa, outb, outc, outd always @ (posedge clk) beginfirsta = a [3:2] seconda = a [1:0] firstb = b [3:2] secondb = b [1:0] endlookup m1 (outa, firsta, firstb, clk), m2 (outb, firsta, secondb, clk), m3 (outc, seconda, firstb, clk), m4 ( outd, seconda, secondb, clk)// module call
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lookup_multi.v