文件名称:quartusII_clock
介绍说明－－下载内容均来自于网络，请自行研究使用
vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
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下载文件列表
5_3
...\03281142.asm.rpt
...\03281142.done
...\03281142.fit.rpt
...\03281142.fit.smsg
...\03281142.fit.summary
...\03281142.flow.rpt
...\03281142.map.rpt
...\03281142.map.summary
...\03281142.pin
...\03281142.pof
...\03281142.qpf
...\03281142.qsf
...\03281142.qws
...\03281142.sof
...\03281142.tan.rpt
...\03281142.tan.summary
...\03281142.tcl
...\altpllpll.cmp
...\altpllpll.ppf
...\altpllpll.vhd
...\altpllpll_0.cmp
...\altpllpll_0.ppf
...\altpllpll_0.vhd
...\Chain1.cdf
...\cpu.ocp
...\cpu.vhd
...\cpu.vho
...\cpu_ic_tag_ram.mif
...\cpu_jtag_debug_module.vhd
...\cpu_jtag_debug_module_wrapper.vhd
...\cpu_mult_cell.vhd
...\cpu_ociram_default_contents.mif
...\cpu_rf_ram_a.mif
...\cpu_rf_ram_b.mif
...\cpu_test_bench.vhd
...\db
...\..\03281142.asm.qmsg
...\..\03281142.cbx.xml
...\..\03281142.cmp.cdb
...\..\03281142.cmp.hdb
...\..\03281142.cmp.kpt
...\..\03281142.cmp.logdb
...\..\03281142.cmp.rdb
...\..\03281142.cmp.tdb
...\..\03281142.cmp0.ddb
...\..\03281142.dbp
...\..\03281142.db_info
...\..\03281142.eco.cdb
...\..\03281142.fit.qmsg
...\..\03281142.hier_info
...\..\03281142.hif
...\..\03281142.map.cdb
...\..\03281142.map.hdb
...\..\03281142.map.logdb
...\..\03281142.map.qmsg
...\..\03281142.pre_map.cdb
...\..\03281142.pre_map.hdb
...\..\03281142.psp
...\..\03281142.pss
...\..\03281142.rtlv.hdb
...\..\03281142.rtlv_sg.cdb
...\..\03281142.rtlv_sg_swap.cdb
...\..\03281142.sgdiff.cdb
...\..\03281142.sgdiff.hdb
...\..\03281142.signalprobe.cdb
...\..\03281142.sld_design_entry.sci
...\..\03281142.sld_design_entry_dsc.sci
...\..\03281142.syn_hier_info
...\..\03281142.tan.qmsg
...\..\altsyncram_00e1.tdf
...\..\altsyncram_10e1.tdf
...\..\altsyncram_8q62.tdf
...\..\altsyncram_kml1.tdf
...\..\altsyncram_nnb1.tdf
...\..\altsyncram_puv1.tdf
...\..\altsyncram_r9e1.tdf
...\..\a_dpfifo_jm21.tdf
...\..\a_fefifo_7cf.tdf
...\..\cntr_bd7.tdf
...\..\cntr_te8.tdf
...\..\decode_lhi.tdf
...\..\dpram_ga21.tdf
...\..\mult_add_1f72.tdf
...\..\scfifo_cg21.tdf
...\jtag_uart.vhd
...\lcd_display.vhd
...\led_pio.vhd
...\nios2.bsf
...\nios2.ptf
...\nios2.v
...\nios2.vhd
...\nios2_generation_script
...\nios2_log.txt
...\nios2_setup_quartus.tcl
...\nios2_sim
...\.........\atail-f.pl
...\.........\cpu_ic_tag_ram.dat
...\.........\cpu_ic_tag_ram.hex
...\.........\cpu_ociram_default_contents.dat
...\03281142.asm.rpt
...\03281142.done
...\03281142.fit.rpt
...\03281142.fit.smsg
...\03281142.fit.summary
...\03281142.flow.rpt
...\03281142.map.rpt
...\03281142.map.summary
...\03281142.pin
...\03281142.pof
...\03281142.qpf
...\03281142.qsf
...\03281142.qws
...\03281142.sof
...\03281142.tan.rpt
...\03281142.tan.summary
...\03281142.tcl
...\altpllpll.cmp
...\altpllpll.ppf
...\altpllpll.vhd
...\altpllpll_0.cmp
...\altpllpll_0.ppf
...\altpllpll_0.vhd
...\Chain1.cdf
...\cpu.ocp
...\cpu.vhd
...\cpu.vho
...\cpu_ic_tag_ram.mif
...\cpu_jtag_debug_module.vhd
...\cpu_jtag_debug_module_wrapper.vhd
...\cpu_mult_cell.vhd
...\cpu_ociram_default_contents.mif
...\cpu_rf_ram_a.mif
...\cpu_rf_ram_b.mif
...\cpu_test_bench.vhd
...\db
...\..\03281142.asm.qmsg
...\..\03281142.cbx.xml
...\..\03281142.cmp.cdb
...\..\03281142.cmp.hdb
...\..\03281142.cmp.kpt
...\..\03281142.cmp.logdb
...\..\03281142.cmp.rdb
...\..\03281142.cmp.tdb
...\..\03281142.cmp0.ddb
...\..\03281142.dbp
...\..\03281142.db_info
...\..\03281142.eco.cdb
...\..\03281142.fit.qmsg
...\..\03281142.hier_info
...\..\03281142.hif
...\..\03281142.map.cdb
...\..\03281142.map.hdb
...\..\03281142.map.logdb
...\..\03281142.map.qmsg
...\..\03281142.pre_map.cdb
...\..\03281142.pre_map.hdb
...\..\03281142.psp
...\..\03281142.pss
...\..\03281142.rtlv.hdb
...\..\03281142.rtlv_sg.cdb
...\..\03281142.rtlv_sg_swap.cdb
...\..\03281142.sgdiff.cdb
...\..\03281142.sgdiff.hdb
...\..\03281142.signalprobe.cdb
...\..\03281142.sld_design_entry.sci
...\..\03281142.sld_design_entry_dsc.sci
...\..\03281142.syn_hier_info
...\..\03281142.tan.qmsg
...\..\altsyncram_00e1.tdf
...\..\altsyncram_10e1.tdf
...\..\altsyncram_8q62.tdf
...\..\altsyncram_kml1.tdf
...\..\altsyncram_nnb1.tdf
...\..\altsyncram_puv1.tdf
...\..\altsyncram_r9e1.tdf
...\..\a_dpfifo_jm21.tdf
...\..\a_fefifo_7cf.tdf
...\..\cntr_bd7.tdf
...\..\cntr_te8.tdf
...\..\decode_lhi.tdf
...\..\dpram_ga21.tdf
...\..\mult_add_1f72.tdf
...\..\scfifo_cg21.tdf
...\jtag_uart.vhd
...\lcd_display.vhd
...\led_pio.vhd
...\nios2.bsf
...\nios2.ptf
...\nios2.v
...\nios2.vhd
...\nios2_generation_script
...\nios2_log.txt
...\nios2_setup_quartus.tcl
...\nios2_sim
...\.........\atail-f.pl
...\.........\cpu_ic_tag_ram.dat
...\.........\cpu_ic_tag_ram.hex
...\.........\cpu_ociram_default_contents.dat