文件名称:11.2
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推荐下载,verilog处理器设计实例.体现了结构描述和寄存器传输描述的应用
-recommend downloading Verilog processor design examples. Reflect the structure descr iption and register transfer described in the Application
-recommend downloading Verilog processor design examples. Reflect the structure descr iption and register transfer described in the Application
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下载文件列表
11.2
....\statemachine.cr.mti
....\statemachine.mpf
....\statemachine.v
....\statemachine.v.bak
....\vsim.wlf
....\wave.do
....\work
....\....\drink_machine
....\....\.............\verilog.asm
....\....\.............\_primary.dat
....\....\.............\_primary.vhd
....\....\_info
....\statemachine.cr.mti
....\statemachine.mpf
....\statemachine.v
....\statemachine.v.bak
....\vsim.wlf
....\wave.do
....\work
....\....\drink_machine
....\....\.............\verilog.asm
....\....\.............\_primary.dat
....\....\.............\_primary.vhd
....\....\_info