文件名称:DDR_SDRAM_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 9927451ddr_sdram_verilog.rar 列表 doc\ddr_sdram.pdf model\mt46v4m16.v route\ddr_sdram.csf route\ddr_sdram.esf route\ddr_sdram.psf route\ddr_sdram.quartus route\ddr_sdram.vqm route\pll1.v simulation\ddr_compile_all.v simulation\ddr_sdram_tb.v simulation\modelsim.ini simulation\readme.txt simulation\work\altclklock\verilog.psm simulation\work\altclklock\_primary.dat simulation\work\altclklock\_primary.vhd simulation\work\ddr_command\verilog.psm simulation\work\ddr_command\_primary.dat simulation\work\ddr_command\_primary.vhd simulation\work\ddr_control_interface\verilog.psm simulation\work\ddr_control_interface\_primary.dat simulation\work\ddr_control_interface\_primary.vhd simulation\work\ddr_data_path\verilog.psm simulation\work\ddr_data_path\_primary.dat simulation\work\ddr_data_path\_primary.vhd simulation\work\ddr_sdram\verilog.psm simulation\work\ddr_sdram\_primary.dat simulation\work\ddr_sdram\_primary.vhd simulation\work\ddr_sdram_tb\verilog.psm simulation\work\ddr_sdram_tb\_primary.dat simulation\work\ddr_sdram_tb\_primary.vhd simulation\work\mt46v4m16\verilog.psm simulation\work\mt46v4m16\_primary.dat simulation\work\mt46v4m16\_primary.vhd simulation\work\pll1\verilog.psm simulation\work\pll1\_primary.dat simulation\work\pll1\_primary.vhd simulation\work\_info source\altclklock.v source\ddr_Command.v source\ddr_control_interface.v source\ddr_data_path.v source\ddr_sdram.v source\Params.v source\pll1.v synthesis\synplicity\ddr_data_path.srm synthesis\synplicity\ddr_data_path.srr synthesis\synplicity\ddr_data_path.srs synthesis\synplicity\ddr_data_path.tlg synthesis\synplicity\ddr_data_path.xrf synthesis\synplicity\ddr_sdram.prj synthesis\synplicity\ddr_sdram.sdc synthesis\synplicity\ddr_sdram.srm synthesis\synplicity\ddr_sdram.srr synthesis\synplicity\ddr_sdram.srs synthesis\synplicity\ddr_sdram.tcl synthesis\synplicity\ddr_sdram.tlg synthesis\synplicity\ddr_sdram.vqm synthesis\synplicity\ddr_sdram.xrf synthesis\synplicity\ddr_sdram_cons.tcl synthesis\synplicity\ddr_sdram_rm.tcl readme.txt simulation\work\altclklock simulation\work\ddr_command simulation\work\ddr_control_interface simulation\work\ddr_data_path simulation\work\ddr_sdram simulation\work\ddr_sdram_tb simulation\work\mt46v4m16 simulation\work\pll1 simulation\work synthesis\synplicity doc model route simulation source synthesis