文件名称:all digital CDR
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- 2022-09-12
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Serial link systems have gradually dominated over parallel link systems in modern
high-speed data link communications. The use of differential signal serial
communications prolongs the length of the data transmission channels, which parallel
communications can not match due to the signal degradation effects caused by, for
example, crosstalk among parallel link wires. In addition, the maximum tolerable skew
among the parallel link wires limits their maximum allowable data transmission speed.
This chapter provides an introduction to serial link systems and also gives an outline of
the thesis, which is devoted to the development of single chip, high-speed, serial link
communications techniques for multi-channel and multi-standard applications.
high-speed data link communications. The use of differential signal serial
communications prolongs the length of the data transmission channels, which parallel
communications can not match due to the signal degradation effects caused by, for
example, crosstalk among parallel link wires. In addition, the maximum tolerable skew
among the parallel link wires limits their maximum allowable data transmission speed.
This chapter provides an introduction to serial link systems and also gives an outline of
the thesis, which is devoted to the development of single chip, high-speed, serial link
communications techniques for multi-channel and multi-standard applications.
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压缩包 : eetop.cn_DPLL.rar 列表 Design and Characteristics of Digital Locked Loops.pdf A 1.0–4.0-Gbps All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control.pdf A 1.6mW 1.6ps-rms-Jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS.pdf A Digital Clock and Data Recovery Architecture for Multi-Gigabitps Binary Links.pdf