文件名称:FPGA实现Jpeg压缩,和视频采集程序

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2020-03-14
  • 文件大小:
  • 101kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • kongqiw*******
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FPGA实现Jpeg压缩,和视频采集程序(Zynq - Main - register access Mio)
相关搜索: fpga

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
fpga-jpeg-verilog\run_length_coding\bench\bench.v.txt 3590 2005-06-16
fpga-jpeg-verilog\run_length_coding\jpeg_rle.v 5863 2005-06-16
fpga-jpeg-verilog\run_length_coding\jpeg_rle1.v 8949 2005-06-16
fpga-jpeg-verilog\run_length_coding\jpeg_rzs.v 6395 2005-06-16
fpga-jpeg-verilog\run_length_coding\attic\jpeg_rle2.v 3529 2005-06-16
fpga-jpeg-verilog\jpeg\bench_top\jpeg_encoder.v 26781 2005-06-16
fpga-jpeg-verilog\jpeg\jpeg_encoder.v 8481 2005-06-16
fpga-jpeg-verilog\jpeg\sim\Makefile.txt 3166 2005-06-16
fpga-jpeg-verilog\jpeg\sim\cds.lib 57 2005-06-16
fpga-jpeg-verilog\jpeg\sim\hdl.var 1076 2005-06-16
fpga-jpeg-verilog\qnr\div_uu.v 5853 2005-06-16
fpga-jpeg-verilog\qnr\jpeg_qnr.v 5211 2005-06-16
fpga-jpeg-verilog\qnr\attic\div.v 5025 2005-06-16
fpga-jpeg-verilog\qnr\attic\div_us.v 3485 2005-06-16
fpga-jpeg-verilog\qnr\attic\ro_cnt.v 3925 2005-06-16
fpga-jpeg-verilog\qnr\attic\ud_cnt.v 3940 2005-06-16
fpga-jpeg-verilog\qnr\div_su.v 4781 2005-06-16
fpga-jpeg-verilog\qnr\bench\bench_div_top.v 4554 2005-06-16
fpga-jpeg-verilog\qnr\bench\timescale.v 23 2005-06-16
fpga-jpeg-verilog\qnr\bench\bench_qnr_top.v 4881 2005-06-16
fpga-jpeg-verilog\rgb2ycrcb\rgb2ycrcb_testbench.v 5323 2005-06-16
fpga-jpeg-verilog\rgb2ycrcb\rgb2ycrcb.v 4751 2005-06-16
fpga-jpeg-verilog\rgb2ycrcb\rgb2ycrcb_webAddress.txt 114 2005-06-16
fpga-jpeg-verilog\rgb2ycrcb\transcript 3008 2005-09-02
fpga-jpeg-verilog\rgb2ycrcb\work\_info 77 2005-09-02
fpga-jpeg-verilog\rgb2ycrcb\rgb2ycrcb.mpf 19073 2005-04-25
fpga-jpeg-verilog\rgb2ycrcb\rgb2ycrcb\_info 77 2005-09-02
fpga-jpeg-verilog\rgb2ycrcb\modelsim.ini 18887 2005-09-02
fpga-jpeg-verilog\rgb2ycrcb\tcl_stacktrace.txt 606 2005-09-02
fpga-jpeg-verilog\dct\dct.v 9321 2005-06-16
fpga-jpeg-verilog\dct\dct_cos_table.v 241692 2005-06-16
fpga-jpeg-verilog\dct\dct_mac.v 4452 2005-06-16
fpga-jpeg-verilog\dct\dct_syn.v 3902 2005-06-16
fpga-jpeg-verilog\dct\dctu.v 3873 2005-06-16
fpga-jpeg-verilog\dct\dctub.v 4688 2005-06-16
fpga-jpeg-verilog\dct\fdct.v 9748 2005-06-16
fpga-jpeg-verilog\dct\zigzag.v 7805 2005-06-16
fpga-jpeg-verilog\dct\ro_cnt.v 3925 2005-06-16
fpga-jpeg-verilog\dct\ud_cnt.v 3940 2005-06-16
fpga-jpeg-verilog\dct\dct_bench\bench_top.v 12773 2005-06-16
fpga-jpeg-verilog\dct\rtl_sim\Makefile.txt 3281 2005-06-16
fpga-jpeg-verilog\dct\huffman\huffman_dec.v 6203 2005-06-16
fpga-jpeg-verilog\dct\huffman\huffman_enc.v 5745 2005-06-16
fpga-jpeg-verilog\dct\huffman\huffman_tables.v 61657 2005-06-16
fpga-jpeg-verilog\dct\huffman\bench\bench_top.v 7371 2005-06-16
fpga-jpeg-verilog\dct\huffman\bench\generic_dpram.v 13237 2005-06-16
fpga-jpeg-verilog\dct\huffman\bench\generic_fifo_lfsr.v 7444 2005-06-16
fpga-jpeg-verilog\dct\huffman\bench\lfsr.v 4026 2005-06-16
fpga-jpeg-verilog\dct\huffman\bench\timescale.v 23 2005-06-16
fpga-jpeg-verilog\dct\huffman\bench 0 2005-06-16
fpga-jpeg-verilog\run_length_coding\bench 0 2005-06-16
fpga-jpeg-verilog\run_length_coding\attic 0 2005-06-16
fpga-jpeg-verilog\jpeg\bench_top 0 2005-06-16
fpga-jpeg-verilog\jpeg\sim 0 2005-06-16
fpga-jpeg-verilog\qnr\attic 0 2005-06-16
fpga-jpeg-verilog\qnr\bench 0 2005-06-16
fpga-jpeg-verilog\rgb2ycrcb\work 0 2005-09-02
fpga-jpeg-verilog\rgb2ycrcb\rgb2ycrcb 0 2005-09-02
fpga-jpeg-verilog\dct\dct_bench 0 2005-06-16
fpga-jpeg-verilog\dct\rtl_sim 0 2005-06-16
fpga-jpeg-verilog\dct\huffman 0 2005-06-16
fpga-jpeg-verilog\run_length_coding 0 2005-06-16
fpga-jpeg-verilog\jpeg 0 2005-06-16
fpga-jpeg-verilog\qnr 0 2005-06-16
fpga-jpeg-verilog\rgb2ycrcb 0 2005-06-16
fpga-jpeg-verilog\dct 0 2005-06-16
fpga-jpeg-verilog 0 2005-11-08

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