文件名称:fpga简易入门代码工程
- 所属分类：
- 其他嵌入式/单片机内容
- 资源属性：
- [源码] [ASM]
- 上传时间：
- 2019-03-17
- 文件大小：
- 28.47mb
- 下载次数：
- 0次
- 提 供 者：
- liusongmei
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : fpga good pro.zip 列表 fpga good pro/ fpga good pro/3fenpin/ fpga good pro/3fenpin/clk_3.asm.rpt fpga good pro/3fenpin/clk_3.done fpga good pro/3fenpin/clk_3.fit.rpt fpga good pro/3fenpin/clk_3.fit.smsg fpga good pro/3fenpin/clk_3.fit.summary fpga good pro/3fenpin/clk_3.flow.rpt fpga good pro/3fenpin/clk_3.map.rpt fpga good pro/3fenpin/clk_3.map.summary fpga good pro/3fenpin/clk_3.pin fpga good pro/3fenpin/clk_3.pof fpga good pro/3fenpin/clk_3.qpf fpga good pro/3fenpin/clk_3.qsf fpga good pro/3fenpin/clk_3.qws fpga good pro/3fenpin/clk_3.sim.rpt fpga good pro/3fenpin/clk_3.sof fpga good pro/3fenpin/clk_3.tan.rpt fpga good pro/3fenpin/clk_3.tan.summary fpga good pro/3fenpin/clk_3.vhd fpga good pro/3fenpin/clk_3.vwf fpga good pro/3fenpin/db/ fpga good pro/3fenpin/db/clk_3.(0).cnf.cdb fpga good pro/3fenpin/db/clk_3.(0).cnf.hdb fpga good pro/3fenpin/db/clk_3.asm.qmsg fpga good pro/3fenpin/db/clk_3.asm_labs.ddb fpga good pro/3fenpin/db/clk_3.cbx.xml fpga good pro/3fenpin/db/clk_3.cmp.cdb fpga good pro/3fenpin/db/clk_3.cmp.hdb fpga good pro/3fenpin/db/clk_3.cmp.kpt fpga good pro/3fenpin/db/clk_3.cmp.logdb fpga good pro/3fenpin/db/clk_3.cmp.rdb fpga good pro/3fenpin/db/clk_3.cmp.tdb fpga good pro/3fenpin/db/clk_3.cmp0.ddb fpga good pro/3fenpin/db/clk_3.cmp2.ddb fpga good pro/3fenpin/db/clk_3.dbp fpga good pro/3fenpin/db/clk_3.db_info fpga good pro/3fenpin/db/clk_3.eco.cdb fpga good pro/3fenpin/db/clk_3.eds_overflow fpga good pro/3fenpin/db/clk_3.fit.qmsg fpga good pro/3fenpin/db/clk_3.fnsim.cdb fpga good pro/3fenpin/db/clk_3.fnsim.hdb fpga good pro/3fenpin/db/clk_3.fnsim.qmsg fpga good pro/3fenpin/db/clk_3.hier_info fpga good pro/3fenpin/db/clk_3.hif fpga good pro/3fenpin/db/clk_3.map.cdb fpga good pro/3fenpin/db/clk_3.map.hdb fpga good pro/3fenpin/db/clk_3.map.logdb fpga good pro/3fenpin/db/clk_3.map.qmsg fpga good pro/3fenpin/db/clk_3.pre_map.cdb fpga good pro/3fenpin/db/clk_3.pre_map.hdb fpga good pro/3fenpin/db/clk_3.psp fpga good pro/3fenpin/db/clk_3.rtlv.hdb fpga good pro/3fenpin/db/clk_3.rtlv_sg.cdb fpga good pro/3fenpin/db/clk_3.rtlv_sg_swap.cdb fpga good pro/3fenpin/db/clk_3.sgdiff.cdb fpga good pro/3fenpin/db/clk_3.sgdiff.hdb fpga good pro/3fenpin/db/clk_3.signalprobe.cdb fpga good pro/3fenpin/db/clk_3.sim.hdb fpga good pro/3fenpin/db/clk_3.sim.qmsg fpga good pro/3fenpin/db/clk_3.sim.rdb fpga good pro/3fenpin/db/clk_3.sim.vwf fpga good pro/3fenpin/db/clk_3.sld_design_entry.sci fpga good pro/3fenpin/db/clk_3.sld_design_entry_dsc.sci fpga good pro/3fenpin/db/clk_3.syn_hier_info fpga good pro/3fenpin/db/clk_3.tan.qmsg fpga good pro/3fenpin/db/wed.zsf fpga good pro/422/ fpga good pro/422/modelsim.ini fpga good pro/422/receiver.vhd fpga good pro/422/tb_receiver.vhd fpga good pro/422/tb_receiver.vhd.bak fpga good pro/422/vsim.wlf fpga good pro/422/work/ fpga good pro/422/work/receiver/ fpga good pro/422/work/receiver/rtl.asm fpga good pro/422/work/receiver/rtl.dat fpga good pro/422/work/receiver/_primary.dat fpga good pro/422/work/tb_receiver/ fpga good pro/422/work/tb_receiver/testbench.asm fpga good pro/422/work/tb_receiver/testbench.dat fpga good pro/422/work/tb_receiver/_primary.dat fpga good pro/422/work/_info fpga good pro/add8/ fpga good pro/add8/cou.asm.rpt fpga good pro/add8/cou.done fpga good pro/add8/cou.fit.rpt fpga good pro/add8/cou.fit.summary fpga good pro/add8/cou.flow.rpt fpga good pro/add8/cou.map.rpt fpga good pro/add8/cou.map.summary fpga good pro/add8/cou.pin fpga good pro/add8/cou.qpf fpga good pro/add8/cou.qsf fpga good pro/add8/cou.qws fpga good pro/add8/cou.sim.rpt fpga good pro/add8/cou.tan.rpt fpga good pro/add8/cou.tan.summary fpga good pro/add8/cou.vwf fpga good pro/add8/db/ fpga good pro/add8/db/cou.cbx.xml fpga good pro/add8/db/cou.cmp.rdb fpga good pro/add8/db/cou.db_info fpga good pro/add8/db/cou.eco.cdb fpga good pro/add8/db/cou.hif fpga good pro/add8/db/cou.map.hdb fpga good pro/add8/db/cou.map.qmsg fpga good pro/add8/db/cou.sld_design_entry.sci fpga good pro/add8/db/cou.sld_design_entry_dsc.sci fpga good pro/add8/db/wed.zsf fpga good pro/add8/Vhdl1.vhd fpga good pro/bdf-7.26/ fpga good pro/bdf-7.26/crc.vhd fpga good pro/bdf-7.26/db/ fpga good pro/bdf-7.26/db/uart.(0).cnf.cdb fpga good pro/bdf-7.26/db/uart.(0).cnf.hdb fpga good pro/bdf-7.26/db/uart.(1).cnf.cdb fpga good pro/bdf-7.26/db/uart.(1).cnf.hdb fpga good pro/bdf-7.26/db/uart.(2).cnf.cdb fpga good pro/bdf-7.26/db/uart.(2).cnf.hdb fpga good pro/bdf-7.26/db/uart.(3).cnf.cdb fpga good pro/bdf-7.26/db/uart.(3).cnf.hdb fpga good pro/bdf-7.26/db/uart.(4).cnf.cdb fpga good pro/bdf-7.26/db/uart.(4).cnf.hdb fpga good pro/bdf-7.26/db/uart.asm.qmsg fpga good pro/bdf-7.26/db/uart.asm_labs.ddb fpga good pro/bdf-7.26/db/uart.cbx.xml fpga good pro/bdf-7.26/db/uart.cmp.cdb fpga good pro/bdf-7.26/db/uart.cmp.hdb fpga good pro/bdf-7.26/db/uart.cmp.kpt fpga good pro/bdf-7.26/db/uart.cmp.logdb fpga good pro/bdf-7.26/db/uart.cmp.rdb fpga good pro/bdf-7.26/db/uart.cmp.tdb fpga good pro/bdf-7.26/db/uart.cmp0.ddb fpga good pro/bdf-7.26/db/uart.cmp2.ddb fpga good pro/bdf-7.26/db/uart.dbp fpga good pro/bdf-7.26/db/uart.db_info fpga good pro/bdf-7.26/db/uart.eco.cdb fpga good pro/bdf-7